command_sync Entity Reference

commond synchronisation More...

Inheritance diagram for command_sync:

Entities
rtl	architecture
	commond synchronisation More...

Libraries
IEEE

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Ports
ipb_clk	in	std_logic
		IPBus clock of 31.25MHz.
out_clk	in	std_logic
		derived from ipb_clk and slower
reset	in	std_logic
		reset
req	in	std_logic
		positive edge sensitive
ack	in	std_logic
		ack
kick	out	std_logic := ' 0 '
		kick downstream state machine

Detailed Description

commond synchronisation

re-synchronises command to output clock using req/ack handshake

Author

Richard Staley

Definition at line 13 of file command_sync.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/command_sync.vhd