eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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Instantiations | Signals
Behavioral Architecture Reference

FPGA Common ID Module. More...

Signals

ipbw  ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr  ipb_rbus_array ( N_SLAVES- 1 downto 0 )

Instantiations

fabric_common_idversion  ipbus_fabric_sel
moduleid  ipbus_ctrlreg_v
xmlversion  ipbus_ctrlreg_v
buildversion  ipbus_ctrlreg_v
firmwareversion  ipbus_ctrlreg_v

Detailed Description

FPGA Common ID Module.

This module provides a number of registers to identify the board and the type and version of the firmware and XML files.

These registers include:

  1. Module ID Register:
    • bit 31: 0 = golden image, 1 = user image
    • bits 30-28: fpga flavour, 0= cFPGA, 1 = pFPGA1, 2 = pFPGA2, 3 = pFPGA3, 4 = pFPGA4
    • bits 27-26: geographic address for process FPGAs only
    • bits 25-20: PCB serial number, control FPGA only
    • bits 19-16: shelf address from IPMC
    • bits 14-12: Slot address, bottom 4 bits
    • bits 11-0: Module code (should be 0xefe)
  2. XML Version Register:
    • version: 32-bit register holding the version of XML files, Major.Minor.Patch
      • bits 31-24: major version
      • bits 24-16: minor version
      • bits 15-0: patch number
    • git_sha: 32-bit register holding the XML Git commit 7-digit SHA of top file
  3. Build Date: 32-bit register holding Firmware build date
  4. Build Time: 32-bit register holding Firmware build time
  5. Firmware Version Register:
    • version: 32-bit register holding the Firmware Version Major.Minor.Patch
      • bits 31-24: major version
      • bits 24-16: minor version
      • bits 15-0: patch number
    • git_sha: 32-bit register holding the Git commit 7-digit SHA of the whole firmware repository
Author
Mohammed Siyad
Saeed Taghavi
Francesco Gonnella

Definition at line 79 of file common_id_registers.vhd.


The documentation for this class was generated from the following file: