first_stage_synch Entity Reference

First Stage Synchronisation of the control FPGA. More...

Inheritance diagram for first_stage_synch:

Entities
Behavioral	architecture
	First Stage Synchronisation of the control FPGA. More...

Libraries
IEEE
xil_defaultlib

Use Clauses
STD_LOGIC_1164
std_logic_arith

Ports
clk160	in	std_logic
		MGT rx clock.
reset	in	std_logic
		reset
mux_cntrl	in	std_logic_vector ( 3 downto 0 )
		first stage mux slect bits
latch_enable	in	std_logic
		latch enable of 128 bits
enable_mgt	in	std_logic
		MGT register enbale.
MGT_Commadet	in	std_logic
		MGT commadet.
commdet_delay	out	std_logic
		MGT commadet pipe.
data_in	in	std_logic_vector ( 31 downto 0 )
		rx data
data_out	out	std_logic_vector ( 128 downto 0 )
		frame data out of 128 bits
crc_error	in	std_logic
		crc error in

Detailed Description

First Stage Synchronisation of the control FPGA.

In the first stage of the synchronisation performs following tasks:

• It measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk and save the value to register.
• Synchronises SIPO in first stage to form a parallel data of the incoming rx data of 160MHz data
• Sets length of pipeline in the first stage, under control of state_machine
• latch when data ready of 128 bits.

Author

Mohammed Siyad

Definition at line 22 of file first_stage_synch.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/first_stage_synch.vhd