Behavioral Architecture Reference

Processes
register_process	( clk )

Signals
prefetched_data	std_logic_vector ( DATA_WIDTH- 1 downto 0 )
middle_data	std_logic_vector ( DATA_WIDTH- 1 downto 0 )
in_ready_sig	std_logic

Detailed Description

Definition at line 26 of file fwft_register.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/fwft_register.vhd