gt_information Entity Reference

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Inheritance diagram for gt_information:

Entities
Behavioral	architecture

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus
ipbus_decode_efex_cntrl_mgt_channel	Package <ipbus_decode_efex_cntrl_mgt_channel>
ipbus_decode_efex_mgt_channel	Package <ipbus_decode_efex_mgt_channel>

Generics
addr_width	natural := 3

Ports
ipb_clk	in	std_logic
		ipbus clock
clk280	in	std_logic
		fabric clock 280MHz
reset	in	std_logic
		reset
ipb_rst	in	std_logic
		ipbus reset
ipb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
ipb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
bc_cntr	in	std_logic_vector ( 4 downto 0 )
		bc cntr value
bc_mux_cntr	in	std_logic_vector ( 4 downto 0 )
		bc value after the mux
delay_cntr	in	std_logic_vector ( 3 downto 0 )
		first stage delay count of gt
not_intable	in	std_logic
		not in the table
tx_pd	in	std_logic
		power control for tx side of the gt
rx_pd	in	std_logic
		power control for rx side of the gt
rx_resetdone	in	std_logic
		rx reset done of the gt if high is done
rx_fsm_resetdone	in	std_logic
		rx fsm reset done of the if high is done
rx_byteisaligned	in	std_logic
		rx byte alignment
tx_resetdone	in	std_logic
		tx reset done of the gt if high is done
tx_fsm_resetdone	in	std_logic
		tx fsm reset done of the gt if high is done
tx_bufstatus	in	std_logic_vector ( 1 downto 0 )
		tx buffer status
rx_realign	in	std_logic
		rx realign status
rx_disperr	in	std_logic
		rx disperr error
crc_error	in	std_logic
		crc_error
BCR_in	in	std_logic
		BCR from TTC information.
clk40	in	std_logic
		fabric clock of 40MHz
rxclk280	in	std_logic
		mgt rxclk
mgtdata_enable	in	std_logic
		mgt enable of the channel
rdy	in	std_logic
		ready to trigger the start of state machanie that controls the playback ram
rxdata	in	std_logic_vector ( 31 downto 0 )
		rx_data from gt channel
ram_data	out	std_logic_vector ( 227 downto 0 )
		kchar generated signal ram_data from the plyback ram gt channel

Detailed Description

Definition at line 19 of file gt_information.vhd.

Member Data Documentation

crc_error

crc_error in std_logic

Port

crc_error

crc error of the gt

Definition at line 64 of file gt_information.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/cntrl_slaves/gt_information.vhd