rtl Architecture Reference

Wrapper for the input spy/playback RAM. More...

Processes
IPBUS_RAM	( clk_ipb )

Components
AlgoInputRAM

Signals
ack	std_logic
ack2	std_logic
ipbus_write	std_logic_vector ( 0 downto 0 )
write_enable	std_logic_vector ( 0 downto 0 )
ipb_out_int	std_logic_vector ( 31 downto 0 )
q_int	std_logic_vector ( 127 downto 0 )

Instantiations
algo_input_ram	algoinputram

Detailed Description

Wrapper for the input spy/playback RAM.

generalised from: ipbus_dpram

Author

Francesco Gonnella

Definition at line 40 of file ipbus_inputRAM_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/ipbus_inputRAM_wrapper.vhd