ipbus_sorting_inputRAM_wrapper Entity Reference

Inheritance diagram for ipbus_sorting_inputRAM_wrapper:

Entities
rtl	architecture

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus
DataTypes	Package <DataTypes>
AlgoDataTypes	Package <AlgoDataTypes>

Ports
clk_ipb	in	std_logic
rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
SortingIn	in	AlgoOutput
BCNIn	in	std_logic_vector ( 11 downto 0 )
SpyBCNIn	in	std_logic := ' 0 '
rclk	in	std_logic
Sync	in	std_logic
we	in	std_logic := ' 0 '
SortingOut	out	AlgoOutput

Detailed Description

Definition at line 14 of file ipbus_sorting_inputRAM_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/ipbus_sorting_inputRAM_wrapper.vhd