rtl Architecture Reference

Processes
IPBUS_RAM	( clk_ipb )
COUNTER_PROC	( rclk )

Components
SortingOutputRAM

Signals
din	std_logic_vector ( 31 downto 0 )
q	std_logic_vector ( 31 downto 0 )
counter	std_logic_vector ( 6 downto 0 ) := " 0000000 "
BC_counter	std_logic_vector ( 3 downto 0 ) := " 0000 "
dSync	std_logic_vector ( 4 downto 0 )
dOutput	AlgoTriggerObjects ( 2 downto 0 )
ack	std_logic
ack2	std_logic
ipbus_write	std_logic_vector ( 0 downto 0 )
write_enable	std_logic_vector ( 0 downto 0 )

Instantiations
algo_output_ram	sortingoutputram

Detailed Description

Definition at line 32 of file ipbus_sorting_outputRAM_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/ipbus_sorting_outputRAM_wrapper.vhd