ipbus_xadc_drp Entity Reference

Inheritance diagram for ipbus_xadc_drp:

Entities
rtl	architecture

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
math_real
ipbus

Generics
NUMREG	natural := 19
reg48	bit_vector ( 15 downto 0 ) := x " 0000 "
reg49	bit_vector ( 15 downto 0 ) := x " 0000 "

Ports
ipb_clk	in	STD_LOGIC
reset	in	STD_LOGIC
VAUXP	in	STD_LOGIC_VECTOR ( 5 downto 0 ) := ( others = > ' 0 ' )
VAUXN	in	STD_LOGIC_VECTOR ( 5 downto 0 ) := ( others = > ' 0 ' )
Vp	in	std_logic
Vn	in	std_logic
ipbus_in	in	ipb_wbus
ipbus_out	out	ipb_rbus

Detailed Description

Definition at line 30 of file ipbus_xadc_drp.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_xadc_drp.vhd