RTL Architecture Reference

Components
MGT11G2_TX_RX_CFPGA_CLOCK_MODULE

Signals
tied_to_ground_i	std_logic
tied_to_vcc_i	std_logic
gt0_txoutclk_i	std_logic
gt0_rxoutclk_i	std_logic
gt1_txoutclk_i	std_logic
gt1_rxoutclk_i	std_logic
gt2_txoutclk_i	std_logic
gt2_rxoutclk_i	std_logic
gt3_txoutclk_i	std_logic
gt3_rxoutclk_i	std_logic
q1_clk1_gtrefclk	std_logic
gt0_txusrclk_i	std_logic
gt0_rxusrclk_i	std_logic
gt1_rxusrclk_i	std_logic
gt2_rxusrclk_i	std_logic
gt3_rxusrclk_i	std_logic

Attributes
syn_noclockbuf	boolean
syn_noclockbuf	signal is true

Instantiations
ibufds_instq1_clk1	ibufds_gte2
txoutclk_bufg0_i	bufh
rxoutclk_bufg0_i	bufh
rxoutclk_bufg1_i	bufh
rxoutclk_bufg2_i	bufh
rxoutclk_bufg3_i	bufh

Detailed Description

Definition at line 111 of file mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd