behavioral Architecture Reference

Processes
PROCESS_56	( clock )

Signals
d_in_s	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
crc_r	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
crc_s	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Detailed Description

Definition at line 18 of file osum_crc9d32.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/osum_crc9d32.vhd