parity_checker Entity Reference

parity checker More...

Inheritance diagram for parity_checker:

Entities
spec	architecture
	parity checker More...

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith

Ports
Clk	in	std_logic
		clock 125 MHz
Data_in	in	std_logic_vector ( 9 downto 0 )
		master rx data with parity bit
Data_out	out	std_logic_vector ( 8 downto 0 )
		master rx data
even_parity	out	std_logic
		parity bit

Detailed Description

parity checker

This module the parity of the incoming data and sets high if there is pariy error

Author

Mohammed Siyad

Definition at line 12 of file parity_checker_spec.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/parity_checker_spec.vhd