synch_stage_1 Entity Reference

First Stage Synchronisation of process FPGA. More...

Inheritance diagram for synch_stage_1:

Entities
Behavioral	architecture
	First Stage Synchronisation of process FPGA. More...

Libraries
IEEE
xil_defaultlib

Use Clauses
STD_LOGIC_1164
std_logic_arith

Ports
clk_280	in	std_logic
		MGT rx clock.
reset	in	std_logic
		reset
mux_cntrl	in	std_logic_vector ( 3 downto 0 )
		first stage mux slect bits
latch_enable	in	std_logic
		latch enable of 226 bits
enable_mgt	in	std_logic
		MGT rx data regsiter enable.
MGT_Commadet	in	std_logic
		MGT commadet.
commdet_delay	out	std_logic := ' 0 '
		MGT commadet pipe.
data_in	in	std_logic_vector ( 31 downto 0 )
		rx data
data_out	out	std_logic_vector ( 227 downto 0 )
		frame data out of 226 bits
align_frame	in	std_logic
		align frame
disperr_error	in	std_logic
		disperr erro
notable_error	in	std_logic
		nottable error
crc_error_in	in	std_logic
		crc error

Detailed Description

First Stage Synchronisation of process FPGA.

In the first stage of the synchronisation performs following tasks:

• It measures the time between the arrival of MGT_commadet and the rising edge of ttc_clk and save the value to register.
• Synchronises SIPO in first stage to form a parallel data of the incoming rx data of 280MHz data
• Sets length of pipeline in the first stage, under control of state_machine
• latch when data ready of 226 bits.

First Stage Synchronisattion

Author

Mohammed Siyad

Definition at line 21 of file synch_stg_1.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/synch_stg_1.vhd