top_udp_config_FPGA Entity Reference

Inheritance diagram for top_udp_config_FPGA:

Entities
struct	architecture

Libraries
ieee
ipbus_lib

Use Clauses
std_logic_1164
std_logic_arith
ipbus
ipbus_trans_decl
mac_arbiter_decl

Generics
IPBUSBUFWIDTH	positive := 6

Ports
ipb_clk	in	std_logic
ipb_in	in	ipb_rbus
hardware_addr	in	std_logic_vector ( 11 DOWNTO 0 )
serial_number	in	std_logic_vector ( 5 DOWNTO 0 ) := ( others = > ' 0 ' )
mac_clk	in	std_logic
mac_rx_data	in	std_logic_vector ( 7 DOWNTO 0 )
mac_rx_error	in	std_logic
mac_rx_last	in	std_logic
mac_rx_valid	in	std_logic
mac_tx_ready	in	std_logic
master_tx_data1	in	std_logic_vector ( 8 DOWNTO 0 )
master_tx_data2	in	std_logic_vector ( 8 DOWNTO 0 )
master_tx_data3	in	std_logic_vector ( 8 DOWNTO 0 )
master_tx_data4	in	std_logic_vector ( 8 DOWNTO 0 )
master_tx_err1	in	std_logic
master_tx_err2	in	std_logic
master_tx_err3	in	std_logic
master_tx_err4	in	std_logic
rst_ipb	in	std_logic
rst_macclk	in	std_logic
p_fpga_reset_125	in	std_logic_vector ( 3 downto 0 )
ipb_out	out	ipb_wbus
mac_tx_data	out	std_logic_vector ( 7 DOWNTO 0 )
mac_tx_error	out	std_logic
mac_tx_last	out	std_logic
mac_tx_valid	out	std_logic
master_rx_data1	out	std_logic_vector ( 8 DOWNTO 0 )
master_rx_data2	out	std_logic_vector ( 8 DOWNTO 0 )
master_rx_data3	out	std_logic_vector ( 8 DOWNTO 0 )
master_rx_data4	out	std_logic_vector ( 8 DOWNTO 0 )
master_tx_pause1	out	STD_LOGIC
master_tx_pause2	out	STD_LOGIC
master_tx_pause3	out	STD_LOGIC
master_tx_pause4	out	STD_LOGIC
master_link_down1	in	std_logic
master_link_down2	in	std_logic
master_link_down3	in	std_logic
master_link_down4	in	std_logic
got_ip_address	out	STD_LOGIC
slaves_ipbus_up	out	std_logic_vector ( 3 downto 0 )

Detailed Description

Definition at line 16 of file top_udp_config_fpga_struct.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/inter_fpga/top_udp_config_fpga_struct.vhd