eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

Back to eFEX documentation
efex_aurora_hub2_gt_common_wrapper.vhd
1 ------------------------------------------------------------------------------/
2 -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
3 --
4 -- This file contains confidential and proprietary information
5 -- of Xilinx, Inc. and is protected under U.S. and
6 -- international copyright and other intellectual property
7 -- laws.
8 --
9 -- DISCLAIMER
10 -- This disclaimer is not a license and does not grant any
11 -- rights to the materials distributed herewith. Except as
12 -- otherwise provided in a valid license issued to you by
13 -- Xilinx, and to the maximum extent permitted by applicable
14 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
15 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
16 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
17 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
18 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
19 -- (2) Xilinx shall not be liable (whether in contract or tort,
20 -- including negligence, or under any other theory of
21 -- liability) for any loss or damage of any kind or nature
22 -- related to, arising under or in connection with these
23 -- materials, including for any direct, or any indirect,
24 -- special, incidental, or consequential loss or damage
25 -- (including loss of data, profits, goodwill, or any type of
26 -- loss or damage suffered as a result of any action brought
27 -- by a third party) even if such damage or loss was
28 -- reasonably foreseeable or Xilinx had been advised of the
29 -- possibility of the same.
30 --
31 -- CRITICAL APPLICATIONS
32 -- Xilinx products are not designed or intended to be fail-
33 -- safe, or for use in any application requiring fail-safe
34 -- performance, such as life-support or safety devices or
35 -- systems, Class III medical devices, nuclear facilities,
36 -- applications related to the deployment of airbags, or any
37 -- other applications that could lead to death, personal
38 -- injury, or severe property or environmental damage
39 -- (individually and collectively, "Critical
40 -- Applications"). Customer assumes the sole risk and
41 -- liability of any use of Xilinx products in Critical
42 -- Applications, subject only to applicable laws and
43 -- regulations governing limitations on product liability.
44 --
45 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
46 -- PART OF THIS FILE AT ALL TIMES.
47 --
48 --
49 --------------------------------------------------------------------------------
50 library IEEE;
51  use IEEE.numeric_std.all;
52  use ieee.std_logic_unsigned.all;
53  use ieee.std_logic_misc.all;
54  use ieee.std_logic_1164.all;
55 
56 library UNISIM;
57  use UNISIM.Vcomponents.ALL;
58 
59 --***************************** Entity Declaration ****************************
60 
61 entity efex_aurora_hub2_gt_common_wrapper is
62 generic
63 (
64  -- Simulation attributes
65  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to "TRUE" to speed up sim reset
66 );
67 port
68 (
69 --____________________________COMMON PORTS ,_______________________________{
70  gt_qpllclk_quad4_i : out std_logic;
71  gt_qpllrefclk_quad4_i : out std_logic;
72  gt_qpllclk_quad5_i : out std_logic;
73  gt_qpllrefclk_quad5_i : out std_logic;
74 --____________________________COMMON PORTS ,_______________________________}
75  ---------------------- Common Block - Ref Clock Ports ---------------------
76  gt0_gtrefclk0_common_in : in std_logic;
77  ------------------------- Common Block - QPLL Ports ------------------------
78  gt0_qplllock_out : out std_logic;
79  gt0_qplllockdetclk_in : in std_logic;
80  gt0_qpllrefclklost_out : out std_logic;
81  gt0_qpllreset_in : in std_logic;
82  ---------------------- Common Block - Ref Clock Ports ---------------------
83  gt1_gtrefclk0_common_in : in std_logic;
84  ------------------------- Common Block - QPLL Ports ------------------------
85  gt1_qplllock_out : out std_logic;
86  gt1_qplllockdetclk_in : in std_logic;
87  gt1_qpllrefclklost_out : out std_logic;
88  gt1_qpllreset_in : in std_logic
89 );
90 
91 end efex_aurora_hub2_gt_common_wrapper;
92 
93 architecture STRUCTURE of efex_aurora_hub2_gt_common_wrapper is
94 
95 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
96  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
97  begin
98  if (qpllfbdiv_top = 16) then
99  return "0000100000";
100  elsif (qpllfbdiv_top = 20) then
101  return "0000110000" ;
102  elsif (qpllfbdiv_top = 32) then
103  return "0001100000" ;
104  elsif (qpllfbdiv_top = 40) then
105  return "0010000000" ;
106  elsif (qpllfbdiv_top = 64) then
107  return "0011100000" ;
108  elsif (qpllfbdiv_top = 66) then
109  return "0101000000" ;
110  elsif (qpllfbdiv_top = 80) then
111  return "0100100000" ;
112  elsif (qpllfbdiv_top = 100) then
113  return "0101110000" ;
114  else
115  return "0000000000" ;
116  end if;
117  end function;
118 
119  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
120  begin
121  if (qpllfbdiv_top = 16) then
122  return '1';
123  elsif (qpllfbdiv_top = 20) then
124  return '1' ;
125  elsif (qpllfbdiv_top = 32) then
126  return '1' ;
127  elsif (qpllfbdiv_top = 40) then
128  return '1' ;
129  elsif (qpllfbdiv_top = 64) then
130  return '1' ;
131  elsif (qpllfbdiv_top = 66) then
132  return '0' ;
133  elsif (qpllfbdiv_top = 80) then
134  return '1' ;
135  elsif (qpllfbdiv_top = 100) then
136  return '1' ;
137  else
138  return '1' ;
139  end if;
140  end function;
141 
142  constant QPLL_FBDIV_TOP : integer := 40;
143  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
144  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
145 
146  -- ground and tied_to_vcc_i signals
147  signal tied_to_ground_i : std_logic;
148  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
149  signal tied_to_vcc_i : std_logic;
150 
151 --********************************* Main Body of Code**************************
152 
153 begin
154 
155 --********************************* Main Body of Code**************************
156  tied_to_ground_i <= '0';
157  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
158  tied_to_vcc_i <= '1';
159 
160 
161  --_________________________________________________________________________
162  --_________________________________________________________________________
163  --_________________________GTHE2_COMMON____________________________________
164 gthe2_common_i : GTHE2_COMMON
165  generic map
166  (
167  -- Simulation attributes
168  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
169  SIM_QPLLREFCLK_SEL => ("001"),
170  SIM_VERSION => ("2.0"),
171 
172 
173  ------------------COMMON BLOCK Attributes---------------
174  BIAS_CFG => (x"0000040000001050"),
175  COMMON_CFG => (x"0000001C"),
176  QPLL_CFG => (x"04801C7"),
177  QPLL_CLKOUT_CFG => ("1111"),
178  QPLL_COARSE_FREQ_OVRD => ("010000"),
179  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
180  QPLL_CP => ("0000011111"),
181  QPLL_CP_MONITOR_EN => ('0'),
182  QPLL_DMONITOR_SEL => ('0'),
183  QPLL_FBDIV => (QPLL_FBDIV_IN),
184  QPLL_FBDIV_MONITOR_EN => ('0'),
185  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
186  QPLL_INIT_CFG => (x"000006"),
187  QPLL_LOCK_CFG => (x"05E8"),
188  QPLL_LPF => ("1111"),
189  QPLL_REFCLK_DIV => (1),
190  RSVD_ATTR0 => (x"0000"),
191  RSVD_ATTR1 => (x"0000"),
192  QPLL_RP_COMP => ('0'),
193  QPLL_VTRL_RESET => ("00"),
194  RCAL_CFG => ("00")
195 
196 
197  )
198  port map
199  (
200  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
201  DRPADDR => tied_to_ground_vec_i(7 downto 0),
202  DRPCLK => tied_to_ground_i,
203  DRPDI => tied_to_ground_vec_i(15 downto 0),
204  DRPDO => open,
205  DRPEN => tied_to_ground_i,
206  DRPRDY => open,
207  DRPWE => tied_to_ground_i,
208  ---------------------- Common Block - Ref Clock Ports ---------------------
209  GTGREFCLK => tied_to_ground_i,
210  GTNORTHREFCLK0 => tied_to_ground_i,
211  GTNORTHREFCLK1 => tied_to_ground_i,
212  GTREFCLK0 => gt0_gtrefclk0_common_in,
213  GTREFCLK1 => tied_to_ground_i,
214  GTSOUTHREFCLK0 => tied_to_ground_i,
215  GTSOUTHREFCLK1 => tied_to_ground_i,
216  ------------------------- Common Block - QPLL Ports ------------------------
217  BGRCALOVRDENB => tied_to_vcc_i,
218  PMARSVDOUT => open,
219  QPLLDMONITOR => open,
220  QPLLFBCLKLOST => open,
221  QPLLLOCK => gt0_qplllock_out,
222  QPLLLOCKDETCLK => gt0_qplllockdetclk_in,
223  QPLLLOCKEN => tied_to_vcc_i,
224  QPLLOUTCLK => gt_qpllclk_quad4_i,
225  QPLLOUTREFCLK => gt_qpllrefclk_quad4_i,
226  QPLLOUTRESET => tied_to_ground_i,
227  QPLLPD => tied_to_vcc_i,
228  QPLLREFCLKLOST => gt0_qpllrefclklost_out,
229  QPLLREFCLKSEL => "001",
230  QPLLRESET => gt0_qpllreset_in,
231  QPLLRSVD1 => "0000000000000000",
232  QPLLRSVD2 => "11111",
233  REFCLKOUTMONITOR => open,
234  ----------------------------- Common Block Ports ---------------------------
235  BGBYPASSB => tied_to_vcc_i,
236  BGMONITORENB => tied_to_vcc_i,
237  BGPDB => tied_to_vcc_i,
238  BGRCALOVRD => "11111",
239  PMARSVD => "00000000",
240  RCALENB => tied_to_vcc_i
241 
242  );
243  --_________________________________________________________________________
244  --_________________________________________________________________________
245  --_________________________GTHE2_COMMON____________________________________
246 gthe2_common_lane1_i : GTHE2_COMMON
247  generic map
248  (
249  -- Simulation attributes
250  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
251  SIM_QPLLREFCLK_SEL => ("001"),
252  SIM_VERSION => ("2.0"),
253 
254 
255  ------------------COMMON BLOCK Attributes---------------
256  BIAS_CFG => (x"0000040000001050"),
257  COMMON_CFG => (x"0000001C"),
258  QPLL_CFG => (x"04801C7"),
259  QPLL_CLKOUT_CFG => ("1111"),
260  QPLL_COARSE_FREQ_OVRD => ("010000"),
261  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
262  QPLL_CP => ("0000011111"),
263  QPLL_CP_MONITOR_EN => ('0'),
264  QPLL_DMONITOR_SEL => ('0'),
265  QPLL_FBDIV => (QPLL_FBDIV_IN),
266  QPLL_FBDIV_MONITOR_EN => ('0'),
267  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
268  QPLL_INIT_CFG => (x"000006"),
269  QPLL_LOCK_CFG => (x"05E8"),
270  QPLL_LPF => ("1111"),
271  QPLL_REFCLK_DIV => (1),
272  RSVD_ATTR0 => (x"0000"),
273  RSVD_ATTR1 => (x"0000"),
274  QPLL_RP_COMP => ('0'),
275  QPLL_VTRL_RESET => ("00"),
276  RCAL_CFG => ("00")
277 
278 
279  )
280  port map
281  (
282  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
283  DRPADDR => tied_to_ground_vec_i(7 downto 0),
284  DRPCLK => tied_to_ground_i,
285  DRPDI => tied_to_ground_vec_i(15 downto 0),
286  DRPDO => open,
287  DRPEN => tied_to_ground_i,
288  DRPRDY => open,
289  DRPWE => tied_to_ground_i,
290  ---------------------- Common Block - Ref Clock Ports ---------------------
291  GTGREFCLK => tied_to_ground_i,
292  GTNORTHREFCLK0 => tied_to_ground_i,
293  GTNORTHREFCLK1 => tied_to_ground_i,
294  GTREFCLK0 => gt1_gtrefclk0_common_in,
295  GTREFCLK1 => tied_to_ground_i,
296  GTSOUTHREFCLK0 => tied_to_ground_i,
297  GTSOUTHREFCLK1 => tied_to_ground_i,
298  ------------------------- Common Block - QPLL Ports ------------------------
299  BGRCALOVRDENB => tied_to_vcc_i,
300  PMARSVDOUT => open,
301  QPLLDMONITOR => open,
302  QPLLFBCLKLOST => open,
303  QPLLLOCK => gt1_qplllock_out,
304  QPLLLOCKDETCLK => gt1_qplllockdetclk_in,
305  QPLLLOCKEN => tied_to_vcc_i,
306  QPLLOUTCLK => gt_qpllclk_quad5_i,
307  QPLLOUTREFCLK => gt_qpllrefclk_quad5_i,
308  QPLLOUTRESET => tied_to_ground_i,
309  QPLLPD => tied_to_vcc_i,
310  QPLLREFCLKLOST => gt1_qpllrefclklost_out,
311  QPLLREFCLKSEL => "001",
312  QPLLRESET => gt1_qpllreset_in,
313  QPLLRSVD1 => "0000000000000000",
314  QPLLRSVD2 => "11111",
315  REFCLKOUTMONITOR => open,
316  ----------------------------- Common Block Ports ---------------------------
317  BGBYPASSB => tied_to_vcc_i,
318  BGMONITORENB => tied_to_vcc_i,
319  BGPDB => tied_to_vcc_i,
320  BGRCALOVRD => "11111",
321  PMARSVD => "00000000",
322  RCALENB => tied_to_vcc_i
323 
324  );
325 
326 end STRUCTURE;
327 
efex_aurora_hub2_gt_common_wrapper.STRUCTURE
Definition: efex_aurora_hub2_gt_common_wrapper.vhd:93
efex_aurora_hub2_gt_common_wrapper
Definition: efex_aurora_hub2_gt_common_wrapper.vhd:61
Generated on Tue Nov 11 2025 09:44:32 for eFEX firmware by   doxygen 1.9.1