ipbus_decode_L1CaloEfexProcessor.vhd

-- Address decode logic for ipbus fabric
-- 
-- This file has been AUTOGENERATED from the address table - do not hand edit
-- 
-- We assume the synthesis tool is clever enough to recognise exclusive conditions
-- in the if statement.
-- 
-- Dave Newbold, February 2011
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
package ipbus_decode_L1CaloEfexProcessor is
 
  constant IPBUS_SEL_WIDTH: positive := 4;
  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
  function ipbus_sel_L1CaloEfexProcessor(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
 
-- START automatically  generated VHDL the Wed Mar  3 14:53:13 2021 
  constant N_SLV_COMMON_ID_VERSION: integer := 0;
  constant N_SLV_COMMON_INFRA: integer := 1;
  constant N_SLV_EFEX_ALGORITHM: integer := 2;
  constant N_SLV_EFEX_SORTING: integer := 3;
  constant N_SLV_EFEX_MGT_TOP: integer := 4;
  constant N_SLV_EFEX_READOUT: integer := 5;
  constant N_SLV_EFEX_LIB_VERSION: integer := 6;
  constant N_SLV_EFEX_MERGING: integer := 7;
  constant N_SLAVES: integer := 8;
-- END automatically generated VHDL
 
    
end ipbus_decode_L1CaloEfexProcessor;
 
package body ipbus_decode_L1CaloEfexProcessor is
 
  function ipbus_sel_L1CaloEfexProcessor(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
    variable sel: ipbus_sel_t;
  begin
 
-- START automatically  generated VHDL the Wed Mar  3 14:53:13 2021 
    if    std_match(addr, "-------------000000-------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_COMMON_ID_VERSION, IPBUS_SEL_WIDTH)); -- common_id_version / base 0x00000000 / mask 0x0007e000
    elsif std_match(addr, "-------------000001-------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_COMMON_INFRA, IPBUS_SEL_WIDTH)); -- common_infra / base 0x00002000 / mask 0x0007e000
    elsif std_match(addr, "-------------00001--------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_EFEX_ALGORITHM, IPBUS_SEL_WIDTH)); -- efex_algorithm / base 0x00004000 / mask 0x0007c000
    elsif std_match(addr, "-------------00010--------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_EFEX_SORTING, IPBUS_SEL_WIDTH)); -- efex_sorting / base 0x00008000 / mask 0x0007c000
    elsif std_match(addr, "-------------010----------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_EFEX_MGT_TOP, IPBUS_SEL_WIDTH)); -- efex_mgt_top / base 0x00020000 / mask 0x00070000
    elsif std_match(addr, "-------------1000---------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_EFEX_READOUT, IPBUS_SEL_WIDTH)); -- efex_readout / base 0x00040000 / mask 0x00078000
    elsif std_match(addr, "-------------101000-------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_EFEX_LIB_VERSION, IPBUS_SEL_WIDTH)); -- efex_lib_version / base 0x00050000 / mask 0x0007e000
    elsif std_match(addr, "-------------10101--------------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_EFEX_MERGING, IPBUS_SEL_WIDTH)); -- efex_merging / base 0x00054000 / mask 0x0007c000
-- END automatically generated VHDL
 
    else
        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
    end if;
 
    return sel;
 
  end function ipbus_sel_L1CaloEfexProcessor;
 
end ipbus_decode_L1CaloEfexProcessor;