ipbus_decode_efex_mgt_quad.vhd

-- Address decode logic for ipbus fabric
-- 
-- This file has been AUTOGENERATED from the address table - do not hand edit
-- 
-- We assume the synthesis tool is clever enough to recognise exclusive conditions
-- in the if statement.
-- 
-- Dave Newbold, February 2011
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
package ipbus_decode_efex_mgt_quad is
 
  constant IPBUS_SEL_WIDTH: positive := 4;
  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
  function ipbus_sel_efex_mgt_quad(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
 
-- START automatically  generated VHDL the Fri Nov 13 12:21:26 2020 
  constant N_SLV_QUAD_MGT_CONTROL: integer := 0;
  constant N_SLV_QUAD_SYNCH_CONTROL: integer := 1;
  constant N_SLV_QUAD_MGT_PULSE: integer := 2;
  constant N_SLV_QUAD_MGT_STATUS: integer := 3;
  constant N_SLV_QUAD_PHASE_CONTROL: integer := 4;
  constant N_SLV_GT0: integer := 5;
  constant N_SLV_GT1: integer := 6;
  constant N_SLV_GT2: integer := 7;
  constant N_SLV_GT3: integer := 8;
  constant N_SLAVES: integer := 9;
-- END automatically generated VHDL
 
    
end ipbus_decode_efex_mgt_quad;
 
package body ipbus_decode_efex_mgt_quad is
 
  function ipbus_sel_efex_mgt_quad(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
    variable sel: ipbus_sel_t;
  begin
 
-- START automatically  generated VHDL the Fri Nov 13 12:21:26 2020 
    if    std_match(addr, "---------------------000-----000") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_QUAD_MGT_CONTROL, IPBUS_SEL_WIDTH)); -- quad.mgt_control / base 0x00000000 / mask 0x00000707
    elsif std_match(addr, "---------------------000-----001") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_QUAD_SYNCH_CONTROL, IPBUS_SEL_WIDTH)); -- quad.synch_control / base 0x00000001 / mask 0x00000707
    elsif std_match(addr, "---------------------000-----010") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_QUAD_MGT_PULSE, IPBUS_SEL_WIDTH)); -- quad.mgt_pulse / base 0x00000002 / mask 0x00000707
    elsif std_match(addr, "---------------------000-----011") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_QUAD_MGT_STATUS, IPBUS_SEL_WIDTH)); -- quad.mgt_status / base 0x00000003 / mask 0x00000707
    elsif std_match(addr, "---------------------000-----100") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_QUAD_PHASE_CONTROL, IPBUS_SEL_WIDTH)); -- quad.phase_control / base 0x00000004 / mask 0x00000707
    elsif std_match(addr, "---------------------001--------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_GT0, IPBUS_SEL_WIDTH)); -- gt0 / base 0x00000100 / mask 0x00000700
    elsif std_match(addr, "---------------------010--------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_GT1, IPBUS_SEL_WIDTH)); -- gt1 / base 0x00000200 / mask 0x00000700
    elsif std_match(addr, "---------------------011--------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_GT2, IPBUS_SEL_WIDTH)); -- gt2 / base 0x00000300 / mask 0x00000700
    elsif std_match(addr, "---------------------100--------") then
      sel := ipbus_sel_t(to_unsigned(N_SLV_GT3, IPBUS_SEL_WIDTH)); -- gt3 / base 0x00000400 / mask 0x00000700
-- END automatically generated VHDL
 
    else
        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
    end if;
 
    return sel;
 
  end function ipbus_sel_efex_mgt_quad;
 
end ipbus_decode_efex_mgt_quad;