Input spy/playback RAM for Algorithm block. More...

Entities
ipbus_inputRAM	entity
	Input spy/playback RAM for Algorithm block. More...

rtl	architecture
	Input spy/playback RAM for Algorithm block. More...

Detailed Description

Input spy/playback RAM for Algorithm block.

This RAM contains algorithm input data, can be used to spy or for playback. Its depth is 16, so data for 16 BCs can be stored or played back. The total width needed to save input data would be 60 TriggerTowers * 11 Layers * 10 bits = 6600 bits. But, In order to make data more human readable, for every of the 60 TTs (110 bits) a RAM having a width of 128 is used so 18 bits must be padded with zeroes. So the actual total width of the RAM is 7680 bits.

The RAM is internally made of 60 128-bit wide RAMs, one for each Trigger Tower. The trigger towers are numbered from 0 to 59 and organized as shown in the following table:

	Eta0	Eta1	Eta2	Eta3	Eta4	Eta5
Phi9	09	19	29	39	49	59
Phi8	08	18	28	38	48	58
Phi7	07	17	27	37	47	57
Phi6	06	16	26	36	46	56
Phi5	05	15	25	35	45	55
Phi4	04	14	24	34	44	54
Phi3	03	13	23	33	43	53
Phi2	02	12	22	32	42	52
Phi1	01	11	21	31	41	51
Phi0	00	10	20	30	40	50

Each one of the 60 128-bit RAMs contains data-words of one trigger tower for 15 BCs padded with zeroes as represented in the following table.

BC	bits 0-9	bits 10-19	bits 20-29	bits 30-31	bits 32-41	bits 42-51	bits 52-61	bits 62-63	bits 64-73	bits 74-83	bits 84-93	bits 94-95	bits 96-105	bits 106-115	bits 116-127
BC 1	L0	L1.0	L1.1	"00"	L1.2	L1.3	L2.0	"00"	L2.1	L2.2	L2.3	"00"	L3	HAD	"000000000000"
BC 2	L0	L1.0	L1.1	"00"	L1.2	L1.3	L2.0	"00"	L2.1	L2.2	L2.3	"00"	L3	HAD	"000000000000"
BC...	L0	L1.0	L1.1	"00"	L1.2	L1.3	L2.0	"00"	L2.1	L2.2	L2.3	"00"	L3	HAD	"000000000000"
BC 16	L0	L1.0	L1.1	"00"	L1.2	L1.3	L2.0	"00"	L2.1	L2.2	L2.3	"00"	L3	HAD	"000000000000"

Were BC n indicates the bunch crossing number and L0, L1.n , L2., L3, and HAD indicate the energy samples for layer 0 (1 data-word), layer 1 (4 data-words), layer 2 (4 data-words), layer 3 (1 word), and hadronic (1 word). All data words are 10-bit wide.

From the ipbus side, each of these 128*16 RAM is remapped into a 32*64 RAM. The ipbus RAM contains data as follows:

BC	bits 0-9	bits 10-19	bits 20-29	bits 30-31
BC 1	L0	L1.0	L1.1	"00"
BC 1	L1.2	L1.3	L2.0	"01"
BC 1	L2.1	L2.2	L2.3	"10"
BC 1	L3	HAD	"000" BCID	"11"

BC 2	L0	L1.0	L1.1	"00"
BC 2	L1.2	L1.3	L2.0	"01"
BC 2	L2.1	L2.2	L2.3	"10"
BC 2	L3	HAD	"000" BCID	"11"

BC...	L0	L1.0	L1.1	"00"
BC...	L1.2	L1.3	L2.0	"01"
BC...	L2.1	L2.2	L2.3	"10"
BC...	L3	HAD	"000" BCID	"11"

BC 16	L0	L1.0	L1.1	"00"
BC 16	L1.2	L1.3	L2.0	"01"
BC 16	L2.1	L2.2	L2.3	"10"
BC 16	L3	HAD	"000" BCID	"11"

As you can see in the entity declaration, the data type used to interface to from this RAM is AlgoInput, being an array of the AlgoTower data structure containing all the 10-bit energy samples of the 4 + hadronic layers. The conversion from this data-structure (AlgoTower) to std_logic_vector is performed by means of two functions to_LogicVector() and to_AlgoInput(). All the data structures and the functions are defined in AlgoDataTypes.vhd, containing all the functions and data-types used to interface to/from the Algorithm and Sorting modules.

Author: Francesco Gonnella

Definition in file ipbus_inputRAM.vhd.

Entities

Detailed Description