ipbus_inputRAM.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library ipbus_lib;
 
use ipbus_lib.ipbus.all;
use work.DataTypes.all;
use work.AlgoDataTypes.all;
library infrastructure_lib;
use infrastructure_lib.EfexDataFormats.all;
 
entity ipbus_inputRAM is
  port(
    clk_ipb : in  std_logic;
    rst     : in  std_logic;
    ipb_in  : in  ipb_wbus;
    ipb_out : out ipb_rbus;
 
    rclk    : in  std_logic;
    Load    : in  std_logic;
    BCNIn   : in  std_logic_vector(11 downto 0);
    AlgoIn  : in  AlgoInput;
    we      : in  std_logic := '0';
    AlgoOut : out AlgoInput;
    BCNOut  : out std_logic_vector(11 downto 0)
    );
 
end ipbus_inputRAM;
 
architecture rtl of ipbus_inputRAM is
 
-- algorithm signals
  signal q                  : std_logic_vector(128*60-1 downto 0);
  signal din                : std_logic_vector(128*60-1 downto 0);
  signal counter            : std_logic_vector(3 downto 0) := "0000";  --16 BCs
  signal L1, L2, L3         : std_logic                    := '0';
 
-- fabric decode signals
  constant BLOCK_WIDTH : integer := 6;  --log2 of the memory address
  signal ipbw : ipb_wbus_array((INPUT_TOWERS - 1) downto 0);
  signal ipbr : ipb_rbus_array((INPUT_TOWERS - 1) downto 0);
 
--  function disable_ram(i : integer) return std_logic is  --only enable RAM for central towers
--  begin
--    if (i >= 12 and i <= 17) or
--      (i >= 22 and i <= 27) or
--      (i >= 32 and i <= 37) or
--      (i >= 42 and i <= 47) then
--      return '0';
--    else
--      return '1';
--    end if;
--  end function;
 
 
begin
 
  fabric_decode : entity ipbus_lib.ipbus_fabric_branch
    generic map(
      NSLV        => INPUT_TOWERS,
      DECODE_BASE => BLOCK_WIDTH
      )
    port map(
      ipb_in          => ipb_in,
      ipb_out         => ipb_out,
      ipb_to_slaves   => ipbw,
      ipb_from_slaves => ipbr
      );
 
  COUNTER_PROC : process(rclk)
  begin
    if rising_edge(rclk) then
      L3 <= L2;                 -- to compensate RAM read latency should be set (at least) 2 clock cycles before Load
      L2 <= L1;                 -- so we delay by 3,
      L1 <= Load;
      if L2 = '1' then
        counter <= std_logic_vector(unsigned(counter) + 1);
      else
        counter <= counter;
      end if;
      --d_counter <= counter;
    end if;
  end process;
 
 
  RAM_FOR : for i in 0 to INPUT_TOWERS-1 generate
    ALGO_INPUT_RAM_WRAPPER : entity work.ipbus_inputRAM_wrapper
      -- generic map(DISABLE => disable_ram(i))
      port map (
        clk_ipb => clk_ipb,
        rst     => rst,
        ipb_in  => ipbw(i),
        ipb_out => ipbr(i),
 
        rclk => rclk,
        din  => din((127+128*i) downto 128*i),
        we   => we and Load  , --this should be synchronous with input data
        q    => q((127+128*i) downto 128*i),
        addr => counter);
  end generate;
 
  -- Conversion between algorithm data-types and std_logic_vectors 
  din     <= to_LogicVector(AlgoIn, BCNIn);
  AlgoOut <= to_AlgoInput(q);
  BCNOut  <= to_BCN(q);
end rtl;