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ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt11g2_tx_rx_cfpga_common.vhd
1 ------------------------------------------------------------------------------/
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : mgt11g2_tx_rx_cfpga_common.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module mgt11g2_tx_rx_cfpga_common
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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62 
63 library ieee;
64 use ieee.std_logic_1164.all;
65 use ieee.numeric_std.all;
66 library UNISIM;
67 use UNISIM.VCOMPONENTS.ALL;
68 
69 --***************************** Entity Declaration ****************************
70 entity mgt11g2_tx_rx_cfpga_common is
71 generic
72 (
73  -- Simulation attributes
74  WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
75  SIM_QPLLREFCLK_SEL : bit_vector := "001"
76 );
77 port
78 (
79  GTGREFCLK_IN : in std_logic;
80  GTNORTHREFCLK0_IN : in std_logic;
81  GTNORTHREFCLK1_IN : in std_logic;
82  GTSOUTHREFCLK0_IN : in std_logic;
83  GTSOUTHREFCLK1_IN : in std_logic;
84  QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
85  GTREFCLK1_IN : in std_logic;
86  GTREFCLK0_IN : in std_logic;
87  QPLLLOCK_OUT : out std_logic;
88  QPLLLOCKDETCLK_IN : in std_logic;
89  QPLLOUTCLK_OUT : out std_logic;
90  QPLLOUTREFCLK_OUT : out std_logic;
91  QPLLREFCLKLOST_OUT : out std_logic;
92  QPLLRESET_IN : in std_logic
93 );
94 
95 end mgt11g2_tx_rx_cfpga_common;
96 
97 architecture RTL of mgt11g2_tx_rx_cfpga_common is
98 
99  attribute CORE_GENERATION_INFO : string;
100  attribute CORE_GENERATION_INFO of RTL : architecture is "mgt11g2_tx_rx_cfpga_common,gtwizard_v3_6_11,{protocol_file=Start_from_scratch}";
101 
102 
103 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
104  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
105  begin
106  if (qpllfbdiv_top = 16) then
107  return "0000100000";
108  elsif (qpllfbdiv_top = 20) then
109  return "0000110000" ;
110  elsif (qpllfbdiv_top = 32) then
111  return "0001100000" ;
112  elsif (qpllfbdiv_top = 40) then
113  return "0010000000" ;
114  elsif (qpllfbdiv_top = 64) then
115  return "0011100000" ;
116  elsif (qpllfbdiv_top = 66) then
117  return "0101000000" ;
118  elsif (qpllfbdiv_top = 80) then
119  return "0100100000" ;
120  elsif (qpllfbdiv_top = 100) then
121  return "0101110000" ;
122  else
123  return "0000000000" ;
124  end if;
125  end function;
126 
127  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
128  begin
129  if (qpllfbdiv_top = 16) then
130  return '1';
131  elsif (qpllfbdiv_top = 20) then
132  return '1' ;
133  elsif (qpllfbdiv_top = 32) then
134  return '1' ;
135  elsif (qpllfbdiv_top = 40) then
136  return '1' ;
137  elsif (qpllfbdiv_top = 64) then
138  return '1' ;
139  elsif (qpllfbdiv_top = 66) then
140  return '0' ;
141  elsif (qpllfbdiv_top = 80) then
142  return '1' ;
143  elsif (qpllfbdiv_top = 100) then
144  return '1' ;
145  else
146  return '1' ;
147  end if;
148  end function;
149  constant QPLL_FBDIV_TOP : integer := 40;
150  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
151  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
152 
153  -- ground and tied_to_vcc_i signals
154  signal tied_to_ground_i : std_logic;
155  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
156  signal tied_to_vcc_i : std_logic;
157  signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
158 begin
159 
160  tied_to_ground_i <= '0';
161  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
162  tied_to_vcc_i <= '1';
163  tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
164 
165  --_________________________________________________________________________
166  --_________________________________________________________________________
167  --_________________________GTXE2_COMMON____________________________________
168 
169  gthe2_common_i : GTHE2_COMMON
170  generic map
171  (
172  -- Simulation attributes
173  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
174  SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
175  SIM_VERSION => "2.0",
176 
177 
178  ------------------COMMON BLOCK Attributes---------------
179  BIAS_CFG => (x"0000040000001050"),
180  COMMON_CFG => (x"0000005C"),
181  QPLL_CFG => (x"04801C7"),
182  QPLL_CLKOUT_CFG => ("1111"),
183  QPLL_COARSE_FREQ_OVRD => ("010000"),
184  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
185  QPLL_CP => ("0000011111"),
186  QPLL_CP_MONITOR_EN => ('0'),
187  QPLL_DMONITOR_SEL => ('0'),
188  QPLL_FBDIV => (QPLL_FBDIV_IN),
189  QPLL_FBDIV_MONITOR_EN => ('0'),
190  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
191  QPLL_INIT_CFG => (x"000006"),
192  QPLL_LOCK_CFG => (x"05E8"),
193  QPLL_LPF => ("1111"),
194  QPLL_REFCLK_DIV => (1),
195  RSVD_ATTR0 => (x"0000"),
196  RSVD_ATTR1 => (x"0000"),
197  QPLL_RP_COMP => ('0'),
198  QPLL_VTRL_RESET => ("00"),
199  RCAL_CFG => ("00")
200 
201 
202  )
203  port map
204  (
205  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
206  DRPADDR => tied_to_ground_vec_i(7 downto 0),
207  DRPCLK => tied_to_ground_i,
208  DRPDI => tied_to_ground_vec_i(15 downto 0),
209  DRPDO => open,
210  DRPEN => tied_to_ground_i,
211  DRPRDY => open,
212  DRPWE => tied_to_ground_i,
213  ---------------------- Common Block - Ref Clock Ports ---------------------
214  GTGREFCLK => GTGREFCLK_IN,
215  GTNORTHREFCLK0 => GTNORTHREFCLK0_IN,
216  GTNORTHREFCLK1 => GTNORTHREFCLK1_IN,
217  GTREFCLK0 => GTREFCLK0_IN,
218  GTREFCLK1 => GTREFCLK1_IN,
219  GTSOUTHREFCLK0 => GTSOUTHREFCLK0_IN,
220  GTSOUTHREFCLK1 => GTSOUTHREFCLK1_IN,
221  ------------------------- Common Block - QPLL Ports -----------------------
222  QPLLDMONITOR => open,
223  ----------------------- Common Block - Clocking Ports ----------------------
224  QPLLOUTCLK => QPLLOUTCLK_OUT,
225  QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
226  REFCLKOUTMONITOR => open,
227  ------------------------- Common Block - QPLL Ports ------------------------
228  BGRCALOVRDENB => tied_to_vcc_i,
229  PMARSVDOUT => open,
230  QPLLFBCLKLOST => open,
231  QPLLLOCK => QPLLLOCK_OUT,
232  QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
233  QPLLLOCKEN => tied_to_vcc_i,
234  QPLLOUTRESET => tied_to_ground_i,
235  QPLLPD => tied_to_ground_i,
236  QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
237  QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
238  QPLLRESET => QPLLRESET_IN,
239  QPLLRSVD1 => "0000000000000000",
240  QPLLRSVD2 => "11111",
241  --------------------------------- QPLL Ports -------------------------------
242  BGBYPASSB => tied_to_vcc_i,
243  BGMONITORENB => tied_to_vcc_i,
244  BGPDB => tied_to_vcc_i,
245  BGRCALOVRD => "11111",
246  PMARSVD => "00000000",
247  RCALENB => tied_to_vcc_i
248 
249  );
250 end RTL;
mgt11g2_tx_rx_cfpga_common.RTL
Definition: mgt11g2_tx_rx_cfpga_common.vhd:97
mgt11g2_tx_rx_cfpga_common
Definition: mgt11g2_tx_rx_cfpga_common.vhd:70
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