startup.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
library UNISIM;
use UNISIM.vcomponents.all;
entity startup is
  port(
    flash_cclk : in std_logic
    );
 
end startup;
architecture rtl of startup is
 
  signal logic0, logic1 : std_logic;
 
begin
 
  logic0 <= '0';
  logic1 <= '1';
 
-- STARTUPE2: STARTUP Block
-- 7 Series
-- Xilinx HDL Libraries Guide, version 14.4
  STARTUPE2_inst : STARTUPE2
    generic map (
      PROG_USR      => "FALSE",
      SIM_CCLK_FREQ => 0.0
      )
    port map (
      CFGCLK    => open,
      CFGMCLK   => open,
      EOS       => open,
      PREQ      => open,
      CLK       => logic0,
      GSR       => logic0,
      GTS       => logic0,
      KEYCLEARB => logic0,
      PACK      => logic0,
      USRCCLKO  => flash_cclk,
      USRCCLKTS => logic0,
      USRDONEO  => logic1,
      USRDONETS => logic1
 
      );
 
end rtl;