My Project  v0.0.16
Signals | Processes | Instantiations
behavior Architecture Reference

Processes

stim_proc  ( )

Signals

CPLD_CLK  std_logic := ' 0 '
HW_ADDR  std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
HW_ADDP  std_logic := ' 0 '
P_ERROR  std_logic := ' 0 '
HW_ATCA  std_logic_vector ( 7 downto 0 )
FORCE_MASTER_n  std_logic := ' 1 '
PL29_Link1_n  std_logic := ' 1 '
HW_ADDR_BUF  std_logic_vector ( 4 downto 0 )
CLOCK_MASTER_n  std_logic
SELECT_HUB_n  std_logic
DRIVE_INFO_n  std_logic
DRIVE_CLOCK_n  std_logic
FP_IPBUS_n  std_logic
FP_IPMC_n  std_logic
HUB1_LED_n  std_logic
NODE_LED_n  std_logic
AERR_LED_n  std_logic
IN_SHELF0_n  STD_LOGIC

Instantiations

uut  ATCA <Entity ATCA>

Member Function Documentation

◆ stim_proc()

stim_proc ( )

Member Data Documentation

◆ AERR_LED_n

AERR_LED_n std_logic
Signal

◆ CLOCK_MASTER_n

CLOCK_MASTER_n std_logic
Signal

◆ CPLD_CLK

CPLD_CLK std_logic := ' 0 '
Signal

◆ DRIVE_CLOCK_n

DRIVE_CLOCK_n std_logic
Signal

◆ DRIVE_INFO_n

DRIVE_INFO_n std_logic
Signal

◆ FORCE_MASTER_n

FORCE_MASTER_n std_logic := ' 1 '
Signal

◆ FP_IPBUS_n

FP_IPBUS_n std_logic
Signal

◆ FP_IPMC_n

FP_IPMC_n std_logic
Signal

◆ HUB1_LED_n

HUB1_LED_n std_logic
Signal

◆ HW_ADDP

HW_ADDP std_logic := ' 0 '
Signal

◆ HW_ADDR

HW_ADDR std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ HW_ADDR_BUF

HW_ADDR_BUF std_logic_vector ( 4 downto 0 )
Signal

◆ HW_ATCA

HW_ATCA std_logic_vector ( 7 downto 0 )
Signal

◆ IN_SHELF0_n

IN_SHELF0_n STD_LOGIC
Signal

◆ NODE_LED_n

NODE_LED_n std_logic
Signal

◆ P_ERROR

P_ERROR std_logic := ' 0 '
Signal

◆ PL29_Link1_n

PL29_Link1_n std_logic := ' 1 '
Signal

◆ SELECT_HUB_n

SELECT_HUB_n std_logic
Signal

◆ uut

uut ATCA
Instantiation

The documentation for this class was generated from the following file: