RTL Architecture Reference

Processes
PROCESS_504	( STABLE_CLOCK , SOFT_RESET )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( STABLE_CLOCK )
PROCESS_505	( TXUSERCLK )
PROCESS_506	( STABLE_CLOCK )
PROCESS_507	( STABLE_CLOCK )
PROCESS_508	( STABLE_CLOCK )
timeout_buffer_bypass	( TXUSERCLK )
timeout_max	( STABLE_CLOCK )
reset_fsm	( STABLE_CLOCK )

Components
CON_2Quads_6g4_sync_block	<Entity CON_2Quads_6g4_sync_block>

Constants
MMCM_LOCK_CNT_MAX	integer := 256
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES + 10
WAIT_TIMEOUT_2ms	integer := 2000000 / STABLE_CLOCK_PERIOD
WAIT_TLOCK_MAX	integer := 100000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_500us	integer := 500000 / STABLE_CLOCK_PERIOD
WAIT_1us_cycles	integer := 1000 / STABLE_CLOCK_PERIOD
WAIT_1us	integer := WAIT_1us_cycles + 10
MAX_RETRIES	integer := 2 ** RETRY_COUNTER_BITWIDTH - 1
MAX_WAIT_BYPASS	integer := 91648
WAIT_TIME_MAX	integer := 100

Types
tx_rst_fsm_type	( INIT , ASSERT_ALL_RESETS , WAIT_FOR_PLL_LOCK , RELEASE_PLL_RESET , WAIT_FOR_TXOUTCLK , RELEASE_MMCM_RESET , WAIT_FOR_TXUSRCLK , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , RESET_FSM_DONE )

Signals
tx_state	tx_rst_fsm_type := INIT
init_wait_count	integer range 0 to WAIT_MAX := 0
init_wait_done	std_logic := ' 0 '
pll_reset_asserted	std_logic := ' 0 '
tx_fsm_reset_done_int	std_logic := ' 0 '
tx_fsm_reset_done_int_s2	std_logic := ' 0 '
tx_fsm_reset_done_int_s3	std_logic := ' 0 '
txresetdone_s2	std_logic := ' 0 '
txresetdone_s3	std_logic := ' 0 '
retry_counter_int	integer range 0 to MAX_RETRIES
time_out_counter	integer range 0 to WAIT_TIMEOUT_2ms := 0
reset_time_out	std_logic := ' 0 '
time_out_2ms	std_logic := ' 0 '
time_tlock_max	std_logic := ' 0 '
time_out_500us	std_logic := ' 0 '
mmcm_lock_count	integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0
mmcm_lock_int	std_logic := ' 0 '
mmcm_lock_i	std_logic := ' 0 '
mmcm_lock_reclocked	std_logic := ' 0 '
run_phase_alignment_int	std_logic := ' 0 '
run_phase_alignment_int_s2	std_logic := ' 0 '
run_phase_alignment_int_s3	std_logic := ' 0 '
wait_bypass_count	integer range 0 to MAX_WAIT_BYPASS - 1
time_out_wait_bypass	std_logic := ' 0 '
time_out_wait_bypass_s2	std_logic := ' 0 '
time_out_wait_bypass_s3	std_logic := ' 0 '
txuserrdy_i	std_logic := ' 0 '
refclk_lost	std_logic
gttxreset_i	std_logic := ' 0 '
txpmaresetdone_i	std_logic := ' 0 '
txpmaresetdone_sync	std_logic
cplllock_sync	std_logic := ' 0 '
qplllock_sync	std_logic := ' 0 '
cplllock_prev	std_logic := ' 0 '
qplllock_prev	std_logic := ' 0 '
cplllock_ris_edge	std_logic := ' 0 '
qplllock_ris_edge	std_logic := ' 0 '
wait_time_cnt	integer range 0 to WAIT_TIME_MAX
wait_time_done	std_logic

Instantiations
sync_run_phase_alignment_int	CON_2Quads_6g4_sync_block <Entity CON_2Quads_6g4_sync_block>
sync_tx_fsm_reset_done_int	CON_2Quads_6g4_sync_block <Entity CON_2Quads_6g4_sync_block>
sync_txresetdone	CON_2Quads_6g4_sync_block <Entity CON_2Quads_6g4_sync_block>
sync_time_out_wait_bypass	CON_2Quads_6g4_sync_block <Entity CON_2Quads_6g4_sync_block>
sync_mmcm_lock_reclocked	CON_2Quads_6g4_sync_block <Entity CON_2Quads_6g4_sync_block>
sync_cplllock	CON_2Quads_6g4_sync_block <Entity CON_2Quads_6g4_sync_block>
sync_qplllock	CON_2Quads_6g4_sync_block <Entity CON_2Quads_6g4_sync_block>

Member Function Documentation

mmcm_lock_wait()

mmcm_lock_wait (   STABLE_CLOCK   )

Process

PROCESS_504()

PROCESS_504 (   STABLE_CLOCK ,   SOFT_RESET   )

Process

PROCESS_505()

PROCESS_505

(

TXUSERCLK

)

PROCESS_506()

PROCESS_506

(

STABLE_CLOCK

)

PROCESS_507()

PROCESS_507

(

STABLE_CLOCK

)

PROCESS_508()

PROCESS_508 (   STABLE_CLOCK   )

Process

reset_fsm()

reset_fsm (   STABLE_CLOCK   )

Process

timeout_buffer_bypass()

timeout_buffer_bypass (   TXUSERCLK   )

Process

timeout_max()

timeout_max (   STABLE_CLOCK   )

Process

timeouts()

timeouts (   STABLE_CLOCK   )

Process

Member Data Documentation

CON_2Quads_6g4_sync_block

CON_2Quads_6g4_sync_block

Component

cplllock_prev

cplllock_prev std_logic := ' 0 '

Signal

cplllock_ris_edge

cplllock_ris_edge std_logic := ' 0 '

Signal

cplllock_sync

cplllock_sync std_logic := ' 0 '

Signal

gttxreset_i

gttxreset_i std_logic := ' 0 '

Signal

init_wait_count

init_wait_count integer range 0 to WAIT_MAX := 0

Signal

init_wait_done

init_wait_done std_logic := ' 0 '

Signal

MAX_RETRIES

MAX_RETRIES integer := 2 ** RETRY_COUNTER_BITWIDTH - 1

Constant

MAX_WAIT_BYPASS

MAX_WAIT_BYPASS integer := 91648

Constant

MMCM_LOCK_CNT_MAX

MMCM_LOCK_CNT_MAX integer := 256

Constant

mmcm_lock_count

mmcm_lock_count integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0

Signal

mmcm_lock_i

mmcm_lock_i std_logic := ' 0 '

Signal

mmcm_lock_int

mmcm_lock_int std_logic := ' 0 '

Signal

mmcm_lock_reclocked

mmcm_lock_reclocked std_logic := ' 0 '

Signal

pll_reset_asserted

pll_reset_asserted std_logic := ' 0 '

Signal

qplllock_prev

qplllock_prev std_logic := ' 0 '

Signal

qplllock_ris_edge

qplllock_ris_edge std_logic := ' 0 '

Signal

qplllock_sync

qplllock_sync std_logic := ' 0 '

Signal

refclk_lost

refclk_lost std_logic

Signal

reset_time_out

reset_time_out std_logic := ' 0 '

Signal

retry_counter_int

retry_counter_int integer range 0 to MAX_RETRIES

Signal

run_phase_alignment_int

run_phase_alignment_int std_logic := ' 0 '

Signal

run_phase_alignment_int_s2

run_phase_alignment_int_s2 std_logic := ' 0 '

Signal

run_phase_alignment_int_s3

run_phase_alignment_int_s3 std_logic := ' 0 '

Signal

STARTUP_DELAY

STARTUP_DELAY integer := 500

Constant

sync_cplllock

sync_cplllock CON_2Quads_6g4_sync_block

Instantiation

sync_mmcm_lock_reclocked

sync_mmcm_lock_reclocked CON_2Quads_6g4_sync_block

Instantiation

sync_qplllock

sync_qplllock CON_2Quads_6g4_sync_block

Instantiation

sync_run_phase_alignment_int

sync_run_phase_alignment_int CON_2Quads_6g4_sync_block

Instantiation

sync_time_out_wait_bypass

sync_time_out_wait_bypass CON_2Quads_6g4_sync_block

Instantiation

sync_tx_fsm_reset_done_int

sync_tx_fsm_reset_done_int CON_2Quads_6g4_sync_block

Instantiation

sync_txresetdone

sync_txresetdone CON_2Quads_6g4_sync_block

Instantiation

time_out_2ms

time_out_2ms std_logic := ' 0 '

Signal

time_out_500us

time_out_500us std_logic := ' 0 '

Signal

time_out_counter

time_out_counter integer range 0 to WAIT_TIMEOUT_2ms := 0

Signal

time_out_wait_bypass

time_out_wait_bypass std_logic := ' 0 '

Signal

time_out_wait_bypass_s2

time_out_wait_bypass_s2 std_logic := ' 0 '

Signal

time_out_wait_bypass_s3

time_out_wait_bypass_s3 std_logic := ' 0 '

Signal

time_tlock_max

time_tlock_max std_logic := ' 0 '

Signal

tx_fsm_reset_done_int

tx_fsm_reset_done_int std_logic := ' 0 '

Signal

tx_fsm_reset_done_int_s2

tx_fsm_reset_done_int_s2 std_logic := ' 0 '

Signal

tx_fsm_reset_done_int_s3

tx_fsm_reset_done_int_s3 std_logic := ' 0 '

Signal

tx_rst_fsm_type

tx_rst_fsm_type ( INIT , ASSERT_ALL_RESETS , WAIT_FOR_PLL_LOCK , RELEASE_PLL_RESET , WAIT_FOR_TXOUTCLK , RELEASE_MMCM_RESET , WAIT_FOR_TXUSRCLK , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , RESET_FSM_DONE )

Type

tx_state

tx_state tx_rst_fsm_type := INIT

Signal

txpmaresetdone_i

txpmaresetdone_i std_logic := ' 0 '

Signal

txpmaresetdone_sync

txpmaresetdone_sync std_logic

Signal

txresetdone_s2

txresetdone_s2 std_logic := ' 0 '

Signal

txresetdone_s3

txresetdone_s3 std_logic := ' 0 '

Signal

txuserrdy_i

txuserrdy_i std_logic := ' 0 '

Signal

WAIT_1us

WAIT_1us integer := WAIT_1us_cycles + 10

Constant

WAIT_1us_cycles

WAIT_1us_cycles integer := 1000 / STABLE_CLOCK_PERIOD

Constant

wait_bypass_count

wait_bypass_count integer range 0 to MAX_WAIT_BYPASS - 1

Signal

WAIT_CYCLES

WAIT_CYCLES integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD

Constant

WAIT_MAX

WAIT_MAX integer := WAIT_CYCLES + 10

Constant

wait_time_cnt

wait_time_cnt integer range 0 to WAIT_TIME_MAX

Signal

wait_time_done

wait_time_done std_logic

Signal

WAIT_TIME_MAX

WAIT_TIME_MAX integer := 100

Constant

WAIT_TIMEOUT_2ms

WAIT_TIMEOUT_2ms integer := 2000000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TIMEOUT_500us

WAIT_TIMEOUT_500us integer := 500000 / STABLE_CLOCK_PERIOD

Constant

WAIT_TLOCK_MAX

WAIT_TLOCK_MAX integer := 100000 / STABLE_CLOCK_PERIOD

Constant

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The documentation for this class was generated from the following file:

• IP/CON_2Quads_6g4/CON_2Quads_6g4/example_design/con_2quads_6g4_tx_startup_fsm.vhd