My Project  v0.0.16
Ports | Libraries | Use Clauses
DOUBLE_RESET Entity Reference
Inheritance diagram for DOUBLE_RESET:
Inheritance graph
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Entities

RTL  architecture
 

Libraries

ieee 
UNISIM 

Use Clauses

std_logic_1164 
numeric_std 
VCOMPONENTS 

Ports

CLK   in std_logic
PLLLKDET   in std_logic
GTXTEST_DONE   out std_logic
GTXTEST_BIT1   out std_logic

Member Data Documentation

◆ CLK

CLK in std_logic
Port

◆ GTXTEST_BIT1

GTXTEST_BIT1 out std_logic
Port

◆ GTXTEST_DONE

GTXTEST_DONE out std_logic
Port

◆ ieee

ieee
Library

◆ numeric_std

numeric_std
Package

◆ PLLLKDET

PLLLKDET in std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ UNISIM

UNISIM
Library

◆ VCOMPONENTS

VCOMPONENTS
Package

The documentation for this class was generated from the following file: