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My Project
v0.0.16
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Entities | |
| RTL | architecture |
Libraries | |
| ieee | |
| UNISIM | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
| VCOMPONENTS | |
Ports | |
| CLK | in std_logic |
| PLLLKDET | in std_logic |
| GTXTEST_DONE | out std_logic |
| GTXTEST_BIT1 | out std_logic |
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Port |
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Port |
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Port |
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Library |
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Package |
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Port |
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Package |
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Library |
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Package |
1.8.13