RTL Architecture Reference

Processes
PROCESS_509	( STABLE_CLOCK )
PROCESS_510	( STABLE_CLOCK )

Components
DSS_3Quads_11g2_sync_block	<Entity DSS_3Quads_11g2_sync_block>

Types
phase_align_auto_fsm	( INIT , WAIT_PHRST_DONE , COUNT_PHALIGN_DONE , PHALIGN_DONE )

Signals
phalign_state	phase_align_auto_fsm := INIT
phaligndone_prev	std_logic := ' 0 '
phaligndone_ris_edge	std_logic
count_phalign_edges	integer range 0 to 3 := 0
phaligndone_sync	std_logic := ' 0 '
dlysresetdone_sync	std_logic := ' 0 '

Instantiations
sync_phaligndone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_dlysresetdone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>

Member Function Documentation

PROCESS_509()

PROCESS_509

(

STABLE_CLOCK

)

PROCESS_510()

PROCESS_510 (   STABLE_CLOCK   )

Process

Member Data Documentation

count_phalign_edges

count_phalign_edges integer range 0 to 3 := 0

Signal

dlysresetdone_sync

dlysresetdone_sync std_logic := ' 0 '

Signal

DSS_3Quads_11g2_sync_block

DSS_3Quads_11g2_sync_block

Component

phalign_state

phalign_state phase_align_auto_fsm := INIT

Signal

phaligndone_prev

phaligndone_prev std_logic := ' 0 '

Signal

phaligndone_ris_edge

phaligndone_ris_edge std_logic

Signal

phaligndone_sync

phaligndone_sync std_logic := ' 0 '

Signal

phase_align_auto_fsm

phase_align_auto_fsm ( INIT , WAIT_PHRST_DONE , COUNT_PHALIGN_DONE , PHALIGN_DONE )

Type

sync_dlysresetdone

sync_dlysresetdone DSS_3Quads_11g2_sync_block

Instantiation

sync_phaligndone

sync_phaligndone DSS_3Quads_11g2_sync_block

Instantiation

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The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_auto_phase_align.vhd