DSS_3Quads_11g2_RX_MANUAL_PHASE_ALIGN Entity Reference

Inheritance diagram for DSS_3Quads_11g2_RX_MANUAL_PHASE_ALIGN:

Collaboration diagram for DSS_3Quads_11g2_RX_MANUAL_PHASE_ALIGN:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Generics
NUMBER_OF_LANES	integer range 1 to 32 := 4
MASTER_LANE_ID	integer range 0 to 31 := 0

Ports
STABLE_CLOCK	in STD_LOGIC
RESET_PHALIGNMENT	in STD_LOGIC
RUN_PHALIGNMENT	in STD_LOGIC
PHASE_ALIGNMENT_DONE	out STD_LOGIC := ' 0 '
RXDLYSRESET	out STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
RXDLYSRESETDONE	in STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 )
RXPHALIGN	out STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
RXPHALIGNDONE	in STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 )
RXDLYEN	out STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Member Data Documentation

IEEE

IEEE

Library

MASTER_LANE_ID

MASTER_LANE_ID integer range 0 to 31 := 0

Generic

NUMBER_OF_LANES

NUMBER_OF_LANES integer range 1 to 32 := 4

Generic

PHASE_ALIGNMENT_DONE

PHASE_ALIGNMENT_DONE out STD_LOGIC := ' 0 '

Port

RESET_PHALIGNMENT

RESET_PHALIGNMENT in STD_LOGIC

Port

RUN_PHALIGNMENT

RUN_PHALIGNMENT in STD_LOGIC

Port

RXDLYEN

RXDLYEN out STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Port

RXDLYSRESET

RXDLYSRESET out STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Port

RXDLYSRESETDONE

RXDLYSRESETDONE in STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 )

Port

RXPHALIGN

RXPHALIGN out STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Port

RXPHALIGNDONE

RXPHALIGNDONE in STD_LOGIC_VECTOR ( NUMBER_OF_LANES - 1 downto 0 )

Port

STABLE_CLOCK

STABLE_CLOCK in STD_LOGIC

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

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The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_manual_phase_align.vhd