RTL Architecture Reference

Processes
PROCESS_511	( STABLE_CLOCK )
PROCESS_512	( STABLE_CLOCK )
PROCESS_513	( STABLE_CLOCK )

Components
DSS_3Quads_11g2_sync_block	<Entity DSS_3Quads_11g2_sync_block>

Constants
VCC_VEC	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 1 ' )
GND_VEC	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Types
rx_phase_align_manual_fsm	( INIT , WAIT_DLYRST_DONE , M_PHALIGN , M_DLYEN , S_PHALIGN , M_DLYEN2 , PHALIGN_DONE )

Signals
rx_phalign_manual_state	rx_phase_align_manual_fsm := INIT
rxphaligndone_prev	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
rxphaligndone_ris_edge	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 )
rxdlysresetdone_store	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
rxphaligndone_store	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
rxdone_clear	std_logic := ' 0 '
rxphaligndone_sync	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
rxdlysresetdone_sync	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
sync_rxphaligndone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_rxdlysresetdone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>

Member Function Documentation

PROCESS_511()

PROCESS_511

(

STABLE_CLOCK

)

PROCESS_512()

PROCESS_512 (   STABLE_CLOCK   )

Process

PROCESS_513()

PROCESS_513 (   STABLE_CLOCK   )

Process

Member Data Documentation

DSS_3Quads_11g2_sync_block

DSS_3Quads_11g2_sync_block

Component

GND_VEC

GND_VEC std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Constant

rx_phalign_manual_state

rx_phalign_manual_state rx_phase_align_manual_fsm := INIT

Signal

rx_phase_align_manual_fsm

rx_phase_align_manual_fsm ( INIT , WAIT_DLYRST_DONE , M_PHALIGN , M_DLYEN , S_PHALIGN , M_DLYEN2 , PHALIGN_DONE )

Type

rxdlysresetdone_store

rxdlysresetdone_store std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

rxdlysresetdone_sync

rxdlysresetdone_sync std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

rxdone_clear

rxdone_clear std_logic := ' 0 '

Signal

rxphaligndone_prev

rxphaligndone_prev std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

rxphaligndone_ris_edge

rxphaligndone_ris_edge std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 )

Signal

rxphaligndone_store

rxphaligndone_store std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

rxphaligndone_sync

rxphaligndone_sync std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

sync_rxdlysresetdone

sync_rxdlysresetdone DSS_3Quads_11g2_sync_block

Instantiation

sync_rxphaligndone

sync_rxphaligndone DSS_3Quads_11g2_sync_block

Instantiation

VCC_VEC

VCC_VEC std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 1 ' )

Constant

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The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_rx_manual_phase_align.vhd