DSS_3Quads_11g2_common Entity Reference

Inheritance diagram for DSS_3Quads_11g2_common:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
WRAPPER_SIM_GTRESET_SPEEDUP	string := " TRUE "
SIM_QPLLREFCLK_SEL	bit_vector := " 001 "

Ports
QPLLREFCLKSEL_IN	in std_logic_vector ( 2 downto 0 )
GTREFCLK1_IN	in std_logic
GTREFCLK0_IN	in std_logic
QPLLLOCK_OUT	out std_logic
QPLLLOCKDETCLK_IN	in std_logic
QPLLOUTCLK_OUT	out std_logic
QPLLOUTREFCLK_OUT	out std_logic
QPLLREFCLKLOST_OUT	out std_logic
QPLLRESET_IN	in std_logic

Member Data Documentation

GTREFCLK0_IN

GTREFCLK0_IN in std_logic

Port

GTREFCLK1_IN

GTREFCLK1_IN in std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

QPLLLOCK_OUT

QPLLLOCK_OUT out std_logic

Port

QPLLLOCKDETCLK_IN

QPLLLOCKDETCLK_IN in std_logic

Port

QPLLOUTCLK_OUT

QPLLOUTCLK_OUT out std_logic

Port

QPLLOUTREFCLK_OUT

QPLLOUTREFCLK_OUT out std_logic

Port

QPLLREFCLKLOST_OUT

QPLLREFCLKLOST_OUT out std_logic

Port

QPLLREFCLKSEL_IN

QPLLREFCLKSEL_IN in std_logic_vector ( 2 downto 0 )

Port

QPLLRESET_IN

QPLLRESET_IN in std_logic

Port

SIM_QPLLREFCLK_SEL

SIM_QPLLREFCLK_SEL bit_vector := " 001 "

Generic

std_logic_1164

std_logic_1164

Package

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

WRAPPER_SIM_GTRESET_SPEEDUP

WRAPPER_SIM_GTRESET_SPEEDUP string := " TRUE "

Generic

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The documentation for this class was generated from the following file:

• FTM/DSS/mgts/dss_3quads_11g2_common.vhd