DSS_3Quads_11g2_sync_pulse Entity Reference

Inheritance diagram for DSS_3Quads_11g2_sync_pulse:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
C_NUM_SRETCH_REGS	integer := 3
C_NUM_SYNC_REGS	integer := 3

Ports
CLK	in STD_LOGIC
USER_DONE	out STD_LOGIC := ' 0 '
GT_DONE	in STD_LOGIC

Member Data Documentation

C_NUM_SRETCH_REGS

C_NUM_SRETCH_REGS integer := 3

Generic

C_NUM_SYNC_REGS

C_NUM_SYNC_REGS integer := 3

Generic

CLK

CLK in STD_LOGIC

Port

GT_DONE

GT_DONE in STD_LOGIC

Port

IEEE

IEEE

Library

NUMERIC_STD

NUMERIC_STD

Package

STD_LOGIC_1164

STD_LOGIC_1164

Package

USER_DONE

USER_DONE out STD_LOGIC := ' 0 '

Port

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The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd