RTL Architecture Reference

Processes
PROCESS_523	( CLK , GT_DONE )
PROCESS_524	( CLK )
PROCESS_525	( CLK )
PROCESS_526	( CLK )

Signals
stretch_r	std_logic_vector ( C_NUM_SRETCH_REGS - 1 downto 0 ) := ( others = > ' 0 ' )
sync1_r	std_logic_vector ( C_NUM_SYNC_REGS - 1 downto 0 ) := ( others = > ' 0 ' )
sync2_r	std_logic_vector ( C_NUM_SYNC_REGS - 1 downto 0 ) := ( others = > ' 0 ' )

Attributes
ASYNC_REG	string
ASYNC_REG	sync1_r : signal is " TRUE "
ASYNC_REG	sync2_r : signal is " TRUE "
shreg_extract	string
shreg_extract	sync1_r : signal is " no "
shreg_extract	sync2_r : signal is " no "

Member Function Documentation

PROCESS_523()

PROCESS_523 (   CLK ,   GT_DONE   )

Process

PROCESS_524()

PROCESS_524 (   CLK   )

Process

PROCESS_525()

PROCESS_525 (   CLK   )

Process

PROCESS_526()

PROCESS_526 (   CLK   )

Process

Member Data Documentation

ASYNC_REG [1/3]

ASYNC_REG string

Attribute

ASYNC_REG [2/3]

ASYNC_REG sync1_r : signal is " TRUE "

Attribute

ASYNC_REG [3/3]

ASYNC_REG sync2_r : signal is " TRUE "

Attribute

shreg_extract [1/3]

shreg_extract string

Attribute

shreg_extract [2/3]

shreg_extract sync1_r : signal is " no "

Attribute

shreg_extract [3/3]

shreg_extract sync2_r : signal is " no "

Attribute

stretch_r

stretch_r std_logic_vector ( C_NUM_SRETCH_REGS - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

sync1_r

sync1_r std_logic_vector ( C_NUM_SYNC_REGS - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

sync2_r

sync2_r std_logic_vector ( C_NUM_SYNC_REGS - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_sync_pulse.vhd