rtl Architecture Reference

Processes
eta_shift_em	( Clk200 , EShiftReg )
eta_shift_tau	( Clk200 , TShiftReg )

Constants
dummy_status	ipb_reg_v ( 0 downto 0 ) := ( others = > x " 00000000 " )

Types
WordArray	( 4 downto 0 ) std_logic_vector ( 9 downto 0 )

Signals
EShiftReg	WordArray
TShiftReg	WordArray
load_algo_sig	std_logic

Instantiations
algorithm_control	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
clock_to_signal	clock_pulse <Entity clock_pulse>

Member Function Documentation

eta_shift_em()

eta_shift_em	(		Clk200,
			EShiftReg
	)

eta_shift_tau()

eta_shift_tau (   Clk200 ,   TShiftReg   )

Process

Member Data Documentation

algorithm_control

algorithm_control ipbus_ctrlreg_v

Instantiation

clock_to_signal

clock_to_signal clock_pulse

Instantiation

dummy_status

dummy_status ipb_reg_v ( 0 downto 0 ) := ( others = > x " 00000000 " )

Constant

EShiftReg

EShiftReg WordArray

Signal

load_algo_sig

load_algo_sig std_logic

Signal

TShiftReg

TShiftReg WordArray

Signal

WordArray

WordArray ( 4 downto 0 ) std_logic_vector ( 9 downto 0 )

Type

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/dummy_algorithm.vhd