clock_pulse Entity Reference

Inheritance diagram for clock_pulse:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164

Ports
CLK_I	in std_logic
RESET	in std_logic := ' 0 '
Enable	in std_logic := ' 1 '
pulse	out std_logic

Member Data Documentation

CLK_I

CLK_I in std_logic

Port

Enable

Enable in std_logic := ' 1 '

Port

ieee

ieee

Library

pulse

pulse out std_logic

Port

RESET

RESET in std_logic := ' 0 '

Port

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following file:

• common/IPbus_SPI/hdl/clock_pulse.vhd