testbench Architecture Reference

Processes
ipbus_stim	( )
control_stim	( )
ipbus_stim	( )
control_stim	( )
ipbus_stim	( )
control_stim	( )

Procedures
	ipbus_cycle( )
	ipbus_null( )
	ipbus_write( )
	ipbus_read( )
	ipbus_cycle( )
	ipbus_write( )
	ipbus_read( )
	ipbus_cycle( )
	ipbus_write( )
	ipbus_read( )

Constants
ipbus_period	time := 32 ns
dclk_period	time := 20 ns
bc_period	time := 25 ns
bc5x_period	time := 5 ns
ALGO_RAM_BASE	integer := 16#400000#
ETOB_RAM_BASE	integer := 16#800000#
N_TXS	positive := 48
N_RXS	positive := 12
WORDSPERFRAME	positive := 7
drp_period	time := 8 ns
ttc_period	time := 25 . 0 ns
mgt_halfperiod	time := ttc_period / ( WORDSPERFRAME * 2 )
bc_halfperiod	time := mgt_halfperiod * WORDSPERFRAME
bc_period	time := bc_halfperiod * 2
TOB_NULL	Frame := ( x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 000000BC " )
TOB_FAKE	Frame := ( x " 000F0B00 " , x " 000F0B01 " , x " 000F0B02 " , x " 000F0B03 " , x " 000F0B04 " , x " 000F0B05 " , x " 000000BC " )
TOB_ERRR	Frame := ( x " 000F0B00 " , x " 000F0B01 " , x " 000F0B02 " , x " 000F0B02 " , x " 000F0B04 " , x " 000F0B05 " , x " 000000BC " )

Types
FRAME	( 0 to 6 ) std_logic_vector ( 31 downto 0 )

Signals
reset	STD_LOGIC := ' 1 '
ipbus_clk	STD_LOGIC := ' 0 '
ipbus_int	ipb_wbus := IPB_WBUS_NULL
ipbus_out	ipb_rbus
mgt_clk	std_logic := ' 0 '
hw_addr	std_logic_vector ( 4 downto 0 )
pll_spi_in	spi_mi
pll_lock	std_logic_vector ( 3 downto 0 )
dss_spin	std_logic := ' 0 '
dss_zero	std_logic := ' 0 '
dclk	STD_LOGIC := ' 0 '
flash_spi_in	spi_mi
clk40M	std_logic := ' 0 '
clk200M	std_logic := ' 0 '
load_algo	std_logic := ' 0 '
ttc_clk	std_logic := ' 0 '
drp_clk	std_logic := ' 0 '
dss_run	std_logic := ' 0 '
mgt_source_clk2	std_logic_vector ( N_TXS - 1 downto 0 )
mgt_source_data	mgt_data_array ( N_TXS - 1 downto 0 )
mgt_sink_clk2	std_logic_vector ( N_RXS - 1 downto 0 )
mgt_sink_data	mgt_data_array ( N_RXS - 1 downto 0 )
data	std_logic_vector ( 31 downto 0 )
ctrl	std_logic_vector ( 3 downto 0 )
mgt_status	mgt_status_array ( 3 downto 0 )
rxdata	std_logic_vector ( 31 downto 0 )
rxctrl	std_logic_vector ( 3 downto 0 )

Instantiations
uut	slaves <Entity slaves>
uut	slaves <Entity slaves>
uut	slaves <Entity slaves>

Member Function Documentation

control_stim() [1/3]

control_stim ( )

Process

control_stim() [2/3]

control_stim ( )

Process

control_stim() [3/3]

control_stim ( )

Process

ipbus_cycle() [1/3]

ipbus_cycle

(

)

ipbus_cycle() [2/3]

ipbus_cycle

(

)

ipbus_cycle() [3/3]

ipbus_cycle

(

)

ipbus_null()

ipbus_null ( )

Procedure

ipbus_read() [1/3]

ipbus_read ( )

Procedure

ipbus_read() [2/3]

ipbus_read ( )

Procedure

ipbus_read() [3/3]

ipbus_read ( )

Procedure

ipbus_stim() [1/3]

ipbus_stim ( )

Process

ipbus_stim() [2/3]

ipbus_stim ( )

Process

ipbus_stim() [3/3]

ipbus_stim ( )

Process

ipbus_write() [1/3]

ipbus_write ( )

Procedure

ipbus_write() [2/3]

ipbus_write ( )

Procedure

ipbus_write() [3/3]

ipbus_write ( )

Procedure

Member Data Documentation

ALGO_RAM_BASE

ALGO_RAM_BASE integer := 16#400000#

Constant

bc5x_period

bc5x_period time := 5 ns

Constant

bc_halfperiod

bc_halfperiod time := mgt_halfperiod * WORDSPERFRAME

Constant

bc_period [1/2]

bc_period time := 25 ns

Constant

bc_period [2/2]

bc_period time := bc_halfperiod * 2

Constant

clk200M

clk200M std_logic := ' 0 '

Signal

clk40M

clk40M std_logic := ' 0 '

Signal

ctrl

ctrl std_logic_vector ( 3 downto 0 )

Signal

data

data std_logic_vector ( 31 downto 0 )

Signal

dclk

dclk STD_LOGIC := ' 0 '

Signal

dclk_period

dclk_period time := 20 ns

Constant

drp_clk

drp_clk std_logic := ' 0 '

Signal

drp_period

drp_period time := 8 ns

Constant

dss_run

dss_run std_logic := ' 0 '

Signal

dss_spin

dss_spin std_logic := ' 0 '

Signal

dss_zero

dss_zero std_logic := ' 0 '

Signal

ETOB_RAM_BASE

ETOB_RAM_BASE integer := 16#800000#

Constant

flash_spi_in

flash_spi_in spi_mi

Signal

FRAME

FRAME ( 0 to 6 ) std_logic_vector ( 31 downto 0 )

Type

hw_addr

hw_addr std_logic_vector ( 4 downto 0 )

Signal

ipbus_clk

ipbus_clk STD_LOGIC := ' 0 '

Signal

ipbus_int

ipbus_int ipb_wbus := IPB_WBUS_NULL

Signal

ipbus_out

ipbus_out ipb_rbus

Signal

ipbus_period

ipbus_period time := 32 ns

Constant

load_algo

load_algo std_logic := ' 0 '

Signal

mgt_clk

mgt_clk std_logic := ' 0 '

Signal

mgt_halfperiod

mgt_halfperiod time := ttc_period / ( WORDSPERFRAME * 2 )

Constant

mgt_sink_clk2

mgt_sink_clk2 std_logic_vector ( N_RXS - 1 downto 0 )

Signal

mgt_sink_data

mgt_sink_data mgt_data_array ( N_RXS - 1 downto 0 )

Signal

mgt_source_clk2

mgt_source_clk2 std_logic_vector ( N_TXS - 1 downto 0 )

Signal

mgt_source_data

mgt_source_data mgt_data_array ( N_TXS - 1 downto 0 )

Signal

mgt_status

mgt_status mgt_status_array ( 3 downto 0 )

Signal

N_RXS

N_RXS positive := 12

Constant

N_TXS

N_TXS positive := 48

Constant

pll_lock

pll_lock std_logic_vector ( 3 downto 0 )

Signal

pll_spi_in

pll_spi_in spi_mi

Signal

reset

reset STD_LOGIC := ' 1 '

Signal

rxctrl

rxctrl std_logic_vector ( 3 downto 0 )

Signal

rxdata

rxdata std_logic_vector ( 31 downto 0 )

Signal

TOB_ERRR

TOB_ERRR Frame := ( x " 000F0B00 " , x " 000F0B01 " , x " 000F0B02 " , x " 000F0B02 " , x " 000F0B04 " , x " 000F0B05 " , x " 000000BC " )

Constant

TOB_FAKE

TOB_FAKE Frame := ( x " 000F0B00 " , x " 000F0B01 " , x " 000F0B02 " , x " 000F0B03 " , x " 000F0B04 " , x " 000F0B05 " , x " 000000BC " )

Constant

TOB_NULL

TOB_NULL Frame := ( x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 0000003C " , x " 000000BC " )

Constant

ttc_clk

ttc_clk std_logic := ' 0 '

Signal

ttc_period

ttc_period time := 25 . 0 ns

Constant

uut [1/3]

uut slaves

Instantiation

uut [2/3]

uut slaves

Instantiation

uut [3/3]

uut slaves

Instantiation

WORDSPERFRAME

WORDSPERFRAME positive := 7

Constant

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The documentation for this class was generated from the following files:

• testbench/IPBus_dss_algo_slave_tb.vhd
• testbench/IPBus_dss_slave_tb.vhd
• testbench/IPBus_dss_slave_watchdog_tb.vhd