slaves Entity Reference

Inheritance diagram for slaves:

Collaboration diagram for slaves:

Entities
rtl	architecture

Libraries
IEEE
UNISIM

Use Clauses
STD_LOGIC_1164
ipbus	Package <ipbus>
numeric_std
ipbus_reg_types	Package <ipbus_reg_types>
ftm	Package <ftm>
ftm_mgt	Package <ftm_mgt>
spi	Package <spi>
ipbus_decode_L1CaloFtm	Package <ipbus_decode_L1CaloFtm>
vcomponents
ipbus_decode_L1CaloFtmDSS	Package <ipbus_decode_L1CaloFtmDSS>
AlgoDataTypes	Package <AlgoDataTypes>
ipbus_decode_address_table_DSS_Algo	Package <ipbus_decode_address_table_DSS_Algo>
ipbus_decode_root	Package <ipbus_decode_root>

Generics
N_TXS	positive
N_RXS	positive
XML_VERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
XML_HASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWDATE	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
GLOBAL_FWTIME	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
FTM_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
FTM_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
IPBUS_LIB_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Ports
ipb_clk	in std_logic
ipb_rst	in std_logic
ipb_in	in ipb_wbus
ipb_out	out ipb_rbus
rst_out	out std_logic
eth_err_ctrl	out std_logic_vector ( 35 downto 0 )
eth_err_stat	in std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
pkt_rx	in std_logic := ' 0 '
pkt_tx	in std_logic := ' 0 '
mgt_clk	in std_logic := ' 0 '
mgt_source_data	out mgt_data_array ( N_TXS - 1 downto 0 )
mgt_source_clk2	in std_logic_vector ( N_TXS - 1 downto 0 )
mgt_sink_data	in mgt_data_array ( N_RXS - 1 downto 0 )
mgt_sink_clk2	in std_logic_vector ( N_RXS - 1 downto 0 )
ttcinfo_data	out mgt_data
ttcinfo_clko	in std_logic
ttcinfo_sink_data	in mgt_data
ttcinfo_sink_clko	in std_logic
drp_clk	in std_logic
mgt_control	out mgt_control_bundle
mgt_status	in mgt_status_bundle
run_dss	out std_logic
hw_addr	in std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ipmc_usrio	in std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
pcb_version	in std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
module_serial_number	out std_logic_vector ( 7 downto 0 )
debug	in std_logic
pll_spi_in	in spi_mi := ( others = > ' 0 ' )
pll_spi_out	out spi_mo
pll_select	out std_logic_vector ( 1 downto 0 )
pll_lock	in std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
pll_powerdn	out std_logic
pll_sync	out std_logic
flash_spi_in	in spi_mi := ( others = > ' 0 ' )
flash_spi_out	out spi_mo
flash_select	out std_logic_vector ( 1 downto 0 )
dss_reprog	out std_logic_vector ( 2 downto 1 )
dss_done	in std_logic_vector ( 2 downto 1 ) := ( others = > ' 0 ' )
dss_init_b	in std_logic_vector ( 2 downto 1 ) := ( others = > ' 0 ' )
dss_reset	out std_logic_vector ( 2 downto 1 )
eeprom_scl	out std_logic
eeprom_sda_o	out std_logic
eeprom_sda_i	in std_logic := ' 0 '
mpod_scl	out std_logic
mpod_sda_o	out std_logic
mpod_sda_i	in std_logic := ' 0 '
bridge_scl	out std_logic
bridge_sda_o	out std_logic
bridge_sda_i	in std_logic := ' 0 '
adcs_scl	out std_logic
adcs_sda_o	out std_logic
adcs_sda_i	in std_logic := ' 0 '
fmc_present_n	in std_logic := ' 0 '
vadj_on	out std_logic
ttc_status	in std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )
ttc_bcrst	in std_logic
ttc_ecr	in std_logic
ttc_l1a	in std_logic
BC_clock	in std_logic
FTM_Orbit	out std_logic
FTM_L1A	out std_logic
fpga_number	in std_logic
ttc_clk	in std_logic := ' 0 '
dss_run	in std_logic := ' 0 '
dss_sync	in std_logic := ' 0 '
clk40M	in std_logic
clk200M	in std_logic
load_algo	in std_logic
sync_dss	in std_logic := ' 0 '
spin_dss	in std_logic := ' 0 '
pkt_ctr_rx	in std_logic
pkt_ctr_tx	in std_logic

Member Data Documentation

adcs_scl

adcs_scl out std_logic

Port

adcs_sda_i

adcs_sda_i in std_logic := ' 0 '

Port

adcs_sda_o

adcs_sda_o out std_logic

Port

AlgoDataTypes

AlgoDataTypes

Package

BC_clock

BC_clock in std_logic

Port

bridge_scl

bridge_scl out std_logic

Port

bridge_sda_i

bridge_sda_i in std_logic := ' 0 '

Port

bridge_sda_o

bridge_sda_o out std_logic

Port

clk200M

clk200M in std_logic

Port

clk40M

clk40M in std_logic

Port

debug

debug in std_logic

Port

drp_clk

drp_clk in std_logic

Port

dss_done

dss_done in std_logic_vector ( 2 downto 1 ) := ( others = > ' 0 ' )

Port

dss_init_b

dss_init_b in std_logic_vector ( 2 downto 1 ) := ( others = > ' 0 ' )

Port

dss_reprog

dss_reprog out std_logic_vector ( 2 downto 1 )

Port

dss_reset

dss_reset out std_logic_vector ( 2 downto 1 )

Port

dss_run

dss_run in std_logic := ' 0 '

Port

dss_sync

dss_sync in std_logic := ' 0 '

Port

eeprom_scl

eeprom_scl out std_logic

Port

eeprom_sda_i

eeprom_sda_i in std_logic := ' 0 '

Port

eeprom_sda_o

eeprom_sda_o out std_logic

Port

eth_err_ctrl

eth_err_ctrl out std_logic_vector ( 35 downto 0 )

Port

eth_err_stat

eth_err_stat in std_logic_vector ( 47 downto 0 ) := X " 000000000000 "

Port

flash_select

flash_select out std_logic_vector ( 1 downto 0 )

Port

flash_spi_in

flash_spi_in in spi_mi := ( others = > ' 0 ' )

Port

flash_spi_out

flash_spi_out out spi_mo

Port

fmc_present_n

fmc_present_n in std_logic := ' 0 '

Port

fpga_number

fpga_number in std_logic

Port

ftm

ftm

Package

FTM_FWHASH

FTM_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

FTM_FWVERSION

FTM_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

FTM_L1A

FTM_L1A out std_logic

Port

ftm_mgt

ftm_mgt

Package

FTM_Orbit

FTM_Orbit out std_logic

Port

GLOBAL_FWDATE

GLOBAL_FWDATE std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

GLOBAL_FWHASH

GLOBAL_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

GLOBAL_FWTIME

GLOBAL_FWTIME std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

GLOBAL_FWVERSION

GLOBAL_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

hw_addr

hw_addr in std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Port

IEEE

IEEE

Library

ipb_clk

ipb_clk in std_logic

Port

ipb_in

ipb_in in ipb_wbus

Port

ipb_out

ipb_out out ipb_rbus

Port

ipb_rst

ipb_rst in std_logic

Port

ipbus

ipbus

Package

ipbus_decode_address_table_DSS_Algo

ipbus_decode_address_table_DSS_Algo

Package

ipbus_decode_L1CaloFtm

ipbus_decode_L1CaloFtm

Package

ipbus_decode_L1CaloFtmDSS

ipbus_decode_L1CaloFtmDSS

Package

ipbus_decode_root

ipbus_decode_root

Package

IPBUS_LIB_FWHASH

IPBUS_LIB_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

ipbus_reg_types

ipbus_reg_types

Package

ipmc_usrio

ipmc_usrio in std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Port

load_algo

load_algo in std_logic

Port

mgt_clk

mgt_clk in std_logic := ' 0 '

Port

mgt_control

mgt_control out mgt_control_bundle

Port

mgt_sink_clk2

mgt_sink_clk2 in std_logic_vector ( N_RXS - 1 downto 0 )

Port

mgt_sink_data

mgt_sink_data in mgt_data_array ( N_RXS - 1 downto 0 )

Port

mgt_source_clk2

mgt_source_clk2 in std_logic_vector ( N_TXS - 1 downto 0 )

Port

mgt_source_data

mgt_source_data out mgt_data_array ( N_TXS - 1 downto 0 )

Port

mgt_status

mgt_status in mgt_status_bundle

Port

module_serial_number

module_serial_number out std_logic_vector ( 7 downto 0 )

Port

mpod_scl

mpod_scl out std_logic

Port

mpod_sda_i

mpod_sda_i in std_logic := ' 0 '

Port

mpod_sda_o

mpod_sda_o out std_logic

Port

N_RXS

N_RXS positive

Generic

N_TXS

N_TXS positive

Generic

numeric_std

numeric_std

Package

pcb_version

pcb_version in std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Port

pkt_ctr_rx

pkt_ctr_rx in std_logic

Port

pkt_ctr_tx

pkt_ctr_tx in std_logic

Port

pkt_rx

pkt_rx in std_logic := ' 0 '

Port

pkt_tx

pkt_tx in std_logic := ' 0 '

Port

pll_lock

pll_lock in std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Port

pll_powerdn

pll_powerdn out std_logic

Port

pll_select

pll_select out std_logic_vector ( 1 downto 0 )

Port

pll_spi_in

pll_spi_in in spi_mi := ( others = > ' 0 ' )

Port

pll_spi_out

pll_spi_out out spi_mo

Port

pll_sync

pll_sync out std_logic

Port

rst_out

rst_out out std_logic

Port

run_dss

run_dss out std_logic

Port

spi

spi

Package

spin_dss

spin_dss in std_logic := ' 0 '

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

sync_dss

sync_dss in std_logic := ' 0 '

Port

ttc_bcrst

ttc_bcrst in std_logic

Port

ttc_clk

ttc_clk in std_logic := ' 0 '

Port

ttc_ecr

ttc_ecr in std_logic

Port

ttc_l1a

ttc_l1a in std_logic

Port

ttc_status

ttc_status in std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )

Port

ttcinfo_clko

ttcinfo_clko in std_logic

Port

ttcinfo_data

ttcinfo_data out mgt_data

Port

ttcinfo_sink_clko

ttcinfo_sink_clko in std_logic

Port

ttcinfo_sink_data

ttcinfo_sink_data in mgt_data

Port

UNISIM

UNISIM

Library

vadj_on

vadj_on out std_logic

Port

vcomponents

vcomponents

Package

XML_HASH

XML_HASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

XML_VERSION

XML_VERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

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The documentation for this class was generated from the following files:

• components/ipbus_util/firmware/hdl/slaves.vhd
• FTM/Control/hdl/slaves_FTM_control.vhd
• FTM/DSS/hdl/slaves_dss.vhd
• FTM/DSS_Algo/hdl/slaves_dss_algo.vhd