rtl Architecture Reference

Processes
PROCESS_408	( ipb_clk )
grab	( ttc_clk )

Constants
NSLV	positive := 6
DPRAM_ADDR_WIDTH	positive := 13
HUB1	std_logic_vector ( 4 downto 0 ) := " 00001 "
MType	std_logic_vector ( 15 downto 0 ) := X " FD55 "
HWrev	std_logic_vector ( 3 downto 0 ) := X " 1 "
NBUF	positive := 32
NSLV	positive := 7

Signals
ipbw	ipb_wbus_array ( NSLV - 1 downto 0 )
ipbr	ipb_rbus_array ( NSLV - 1 downto 0 )
ipbr_d	ipb_rbus_array ( NSLV - 1 downto 0 )
ctrl_reg	std_logic_vector ( 31 downto 0 )
inj_ctrl	std_logic_vector ( 63 downto 0 )
inj_stat	std_logic_vector ( 63 downto 0 )
ipbw	ipb_wbus_array ( N_SLAVES - 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES - 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES - 1 downto 0 )
sync_frame	std_logic
run_playback	std_logic
run_source	std_logic
run_sink	std_logic
run_dss_int	std_logic
capture_rx	std_logic
ftm_bcr	std_logic
ftm_bcr_delayed	std_logic
ftm_bcr_backplane	std_logic
bcrst_hub_or_node	std_logic
xcvr_ctrl_reg	ipb_reg_v ( 1 downto 0 )
xcvr_status	ipb_reg_v ( 1 downto 0 )
eeprom_scl_int	std_logic
eeprom_sda_o_int	std_logic
eeprom_sda_i_int	std_logic
retrieved_data	std_logic_vector ( 63 downto 0 )
ctrl_reg	ipb_reg_v ( 1 downto 0 )
trigger	std_logic_vector ( 31 downto 0 )
module_status	ipb_reg_v ( 0 downto 0 )
ttc_status_array	ipb_reg_v ( 3 downto 0 )
ttc_mgt	ttc_mgt_channel_status
pll_sync_int	std_logic
pll_lock_int	std_logic_vector ( 3 downto 0 )
FTM_L1A_i	std_logic
local_l1a	std_logic
ttc_mgt_rx_ok	std_logic := ' 1 '
BC_clock_fake	std_logic
HW_Position	std_logic_vector ( 31 downto 0 )
Module_ID	std_logic_vector ( 31 downto 0 )
PCBissue	std_logic_vector ( 3 downto 0 )
PCBsn	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ttc_info_delay	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
FTM_ECR	std_logic := ' 0 '
xcvr_status	ipb_reg_v ( 7 downto 0 )
sync_frame_i	std_logic
run_in	std_logic
frame_type	std_logic_vector ( 2 downto 0 )
rxon	std_logic_vector ( 3 downto 0 )
loopback_mode	std_logic_vector ( 2 downto 0 )
rstrx	std_logic_vector ( 3 downto 0 )
rsttx	std_logic_vector ( 3 downto 0 )
FPGA_Position	std_logic_vector ( 3 downto 0 )
reset_algo	std_logic := ' 0 '
algo_data	Algo2DInput
etob_data	AlgoOutput
ttob_data	AlgoOutput
ttc_sync	std_logic
ttc_spin	std_logic
tob_sync	std_logic
tob_spin	std_logic

Attributes
mark_debug	string
mark_debug	ttcinfo_sink_data : signal is " true "

Instantiations
fabric	ipbus_fabric <Entity ipbus_fabric>
slave0	ipbus_ctrlreg
slave1	ipbus_reg
slave3	ipbus_ctrlreg
slave5	ipbus_pkt_ctr <Entity ipbus_pkt_ctr>
slave2	ipbus_ram <Entity ipbus_ram>
slave4	ipbus_peephole_ram <Entity ipbus_peephole_ram>
fabric	ipbus_fabric_sel <Entity ipbus_fabric_sel>
fpga_id	ipbus_ftm_fpga_id_version <Entity ipbus_ftm_fpga_id_version>
module_control	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
spi_pll	ipbus_spi32 <Entity ipbus_spi32>
spi_flash	ipbus_spi32 <Entity ipbus_spi32>
xcvr_control	ipbus_con_xcvr_control <Entity ipbus_con_xcvr_control>
buffer_control	ipbus_ftm_buffer_control <Entity ipbus_ftm_buffer_control>
ttc_info	ipbus_ttcinfo <Entity ipbus_ttcinfo>
clock_to_signal	clock_pulse <Entity clock_pulse>
tx_bufs	ipbus_mgt_source <Entity ipbus_mgt_source>
rx_bufs	ipbus_mgt_sink <Entity ipbus_mgt_sink>
ttc	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
configure	ipbus_self_configure <Entity ipbus_self_configure>
monitoring	ipbus_xadc_array <Entity ipbus_xadc_array>
i2c_eeprom	ipbus_i2c_master_arb <Entity ipbus_i2c_master_arb>
address_reader	eeprom_addr_reader <Entity eeprom_addr_reader>
i2c_mpod	ipbus_i2c_master_arb <Entity ipbus_i2c_master_arb>
i2c_bridge	ipbus_i2c_master_arb <Entity ipbus_i2c_master_arb>
i2c_adcs	ipbus_i2c_master_arb <Entity ipbus_i2c_master_arb>
playback_control	ipbus_module_playback <Entity ipbus_module_playback>
l1a_generator	ipbus_L1A_Generator <Entity ipbus_L1A_Generator>
fabric	ipbus_fabric_sel <Entity ipbus_fabric_sel>
module_id	ipbus_ftm_fpga_id_version <Entity ipbus_ftm_fpga_id_version>
fpga_control	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
spi_flash	ipbus_spi32 <Entity ipbus_spi32>
configure	ipbus_self_configure <Entity ipbus_self_configure>
monitoring	ipbus_xadc_array <Entity ipbus_xadc_array>
xcvr_control	ipbus_dss_xcvr_control <Entity ipbus_dss_xcvr_control>
buffer_control	ipbus_dss_buffer_control <Entity ipbus_dss_buffer_control>
tx_bufs	ipbus_mgt_source <Entity ipbus_mgt_source>
rx_bufs	ipbus_mgt_sink_ref <Entity ipbus_mgt_sink_ref>
rx_error_monitors	ipbus_mgt_error_counters <Entity ipbus_mgt_error_counters>
fabric	ipbus_fabric_sel <Entity ipbus_fabric_sel>
fw_version	ipbus_fw_version <Entity ipbus_fw_version>
fpga_control	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
spi_flash	ipbus_spi32 <Entity ipbus_spi32>
configure	ipbus_self_configure <Entity ipbus_self_configure>
monitoring	ipbus_xadc_array <Entity ipbus_xadc_array>
pointer_control	ipbus_algo_master_pointers <Entity ipbus_algo_master_pointers>
algo_input_source	ipbus_algo_source <Entity ipbus_algo_source>
etob_output_sink	ipbus_tob_sink <Entity ipbus_tob_sink>
ttob_output_sink	ipbus_tob_sink <Entity ipbus_tob_sink>
algorithm_interface	IPBusTopAlgoModule <Entity IPBusTopAlgoModule>
fabric	ipbus_fabric_sel <Entity ipbus_fabric_sel>
slave0	ipbus_ctrlreg
fabric	ipbus_fabric <Entity ipbus_fabric>
slave0	ipbus_ctrlreg
slave1	ipbus_reg
slave3	ipbus_ctrlreg
slave5	ipbus_pkt_ctr <Entity ipbus_pkt_ctr>
slave2	ipbus_ram <Entity ipbus_ram>
slave4	ipbus_peephole_ram <Entity ipbus_peephole_ram>
fabric	ipbus_fabric <Entity ipbus_fabric>
slave0	ipbus_ctrlreg
slave1	ipbus_reg
slave3	ipbus_ctrlreg
slave5	ipbus_peephole_ram <Entity ipbus_peephole_ram>
slave6	ipbus_pkt_ctr <Entity ipbus_pkt_ctr>
slave2	ipbus_ram <Entity ipbus_ram>
fabric	ipbus_fabric <Entity ipbus_fabric>
slave0	ipbus_ctrlreg
slave1	ipbus_reg
slave3	ipbus_ctrlreg
slave5	ipbus_pkt_ctr <Entity ipbus_pkt_ctr>
slave2	ipbus_ram <Entity ipbus_ram>
slave4	ipbus_peephole_ram <Entity ipbus_peephole_ram>

Member Function Documentation

grab()

grab (   ttc_clk   )

Process

PROCESS_408()

PROCESS_408

(

ipb_clk

)

Member Data Documentation

address_reader

address_reader eeprom_addr_reader

Instantiation

algo_data

algo_data Algo2DInput

Signal

algo_input_source

algo_input_source ipbus_algo_source

Instantiation

algorithm_interface

algorithm_interface IPBusTopAlgoModule

Instantiation

BC_clock_fake

BC_clock_fake std_logic

Signal

bcrst_hub_or_node

bcrst_hub_or_node std_logic

Signal

buffer_control [1/2]

buffer_control ipbus_dss_buffer_control

Instantiation

buffer_control [2/2]

buffer_control ipbus_ftm_buffer_control

Instantiation

capture_rx

capture_rx std_logic

Signal

clock_to_signal

clock_to_signal clock_pulse

Instantiation

configure [1/3]

configure ipbus_self_configure

Instantiation

configure [2/3]

configure ipbus_self_configure

Instantiation

configure [3/3]

configure ipbus_self_configure

Instantiation

ctrl_reg [1/2]

ctrl_reg std_logic_vector ( 31 downto 0 )

Signal

ctrl_reg [2/2]

ctrl_reg ipb_reg_v ( 1 downto 0 )

Signal

DPRAM_ADDR_WIDTH

DPRAM_ADDR_WIDTH positive := 13

Constant

eeprom_scl_int

eeprom_scl_int std_logic

Signal

eeprom_sda_i_int

eeprom_sda_i_int std_logic

Signal

eeprom_sda_o_int

eeprom_sda_o_int std_logic

Signal

etob_data

etob_data AlgoOutput

Signal

etob_output_sink

etob_output_sink ipbus_tob_sink

Instantiation

fabric [1/8]

fabric ipbus_fabric

Instantiation

fabric [2/8]

fabric ipbus_fabric

Instantiation

fabric [3/8]

fabric ipbus_fabric

Instantiation

fabric [4/8]

fabric ipbus_fabric

Instantiation

fabric [5/8]

fabric ipbus_fabric_sel

Instantiation

fabric [6/8]

fabric ipbus_fabric_sel

Instantiation

fabric [7/8]

fabric ipbus_fabric_sel

Instantiation

fabric [8/8]

fabric ipbus_fabric_sel

Instantiation

fpga_control [1/2]

fpga_control ipbus_ctrlreg_v

Instantiation

fpga_control [2/2]

fpga_control ipbus_ctrlreg_v

Instantiation

fpga_id

fpga_id ipbus_ftm_fpga_id_version

Instantiation

FPGA_Position

FPGA_Position std_logic_vector ( 3 downto 0 )

Signal

frame_type

frame_type std_logic_vector ( 2 downto 0 )

Signal

ftm_bcr

ftm_bcr std_logic

Signal

ftm_bcr_backplane

ftm_bcr_backplane std_logic

Signal

ftm_bcr_delayed

ftm_bcr_delayed std_logic

Signal

FTM_ECR

FTM_ECR std_logic := ' 0 '

Signal

FTM_L1A_i

FTM_L1A_i std_logic

Signal

fw_version

fw_version ipbus_fw_version

Instantiation

HUB1

HUB1 std_logic_vector ( 4 downto 0 ) := " 00001 "

Constant

HW_Position

HW_Position std_logic_vector ( 31 downto 0 )

Signal

HWrev

HWrev std_logic_vector ( 3 downto 0 ) := X " 1 "

Constant

i2c_adcs

i2c_adcs ipbus_i2c_master_arb

Instantiation

i2c_bridge

i2c_bridge ipbus_i2c_master_arb

Instantiation

i2c_eeprom

i2c_eeprom ipbus_i2c_master_arb

Instantiation

i2c_mpod

i2c_mpod ipbus_i2c_master_arb

Instantiation

inj_ctrl

inj_ctrl std_logic_vector ( 63 downto 0 )

Signal

inj_stat

inj_stat std_logic_vector ( 63 downto 0 )

Signal

ipbr [1/2]

ipbr ipb_rbus_array ( NSLV - 1 downto 0 )

Signal

ipbr [2/2]

ipbr ipb_rbus_array ( N_SLAVES - 1 downto 0 )

Signal

ipbr_d [1/2]

ipbr_d ipb_rbus_array ( NSLV - 1 downto 0 )

Signal

ipbr_d [2/2]

ipbr_d ipb_rbus_array ( N_SLAVES - 1 downto 0 )

Signal

ipbw [1/2]

ipbw ipb_wbus_array ( NSLV - 1 downto 0 )

Signal

ipbw [2/2]

ipbw ipb_wbus_array ( N_SLAVES - 1 downto 0 )

Signal

l1a_generator

l1a_generator ipbus_L1A_Generator

Instantiation

local_l1a

local_l1a std_logic

Signal

loopback_mode

loopback_mode std_logic_vector ( 2 downto 0 )

Signal

mark_debug [1/2]

mark_debug string

Attribute

mark_debug [2/2]

mark_debug ttcinfo_sink_data : signal is " true "

Attribute

module_control

module_control ipbus_ctrlreg_v

Instantiation

module_id

module_id ipbus_ftm_fpga_id_version

Instantiation

Module_ID

Module_ID std_logic_vector ( 31 downto 0 )

Signal

module_status

module_status ipb_reg_v ( 0 downto 0 )

Signal

monitoring [1/3]

monitoring ipbus_xadc_array

Instantiation

monitoring [2/3]

monitoring ipbus_xadc_array

Instantiation

monitoring [3/3]

monitoring ipbus_xadc_array

Instantiation

MType

MType std_logic_vector ( 15 downto 0 ) := X " FD55 "

Constant

NBUF

NBUF positive := 32

Constant

NSLV [1/2]

NSLV positive := 7

Constant

NSLV [2/2]

NSLV positive := 6

Constant

PCBissue

PCBissue std_logic_vector ( 3 downto 0 )

Signal

PCBsn

PCBsn std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

playback_control

playback_control ipbus_module_playback

Instantiation

pll_lock_int

pll_lock_int std_logic_vector ( 3 downto 0 )

Signal

pll_sync_int

pll_sync_int std_logic

Signal

pointer_control

pointer_control ipbus_algo_master_pointers

Instantiation

reset_algo

reset_algo std_logic := ' 0 '

Signal

retrieved_data

retrieved_data std_logic_vector ( 63 downto 0 )

Signal

rstrx

rstrx std_logic_vector ( 3 downto 0 )

Signal

rsttx

rsttx std_logic_vector ( 3 downto 0 )

Signal

run_dss_int

run_dss_int std_logic

Signal

run_in

run_in std_logic

Signal

run_playback

run_playback std_logic

Signal

run_sink

run_sink std_logic

Signal

run_source

run_source std_logic

Signal

rx_bufs [1/2]

rx_bufs ipbus_mgt_sink_ref

Instantiation

rx_bufs [2/2]

rx_bufs ipbus_mgt_sink

Instantiation

rx_error_monitors

rx_error_monitors ipbus_mgt_error_counters

Instantiation

rxon

rxon std_logic_vector ( 3 downto 0 )

Signal

slave0 [1/5]

slave0 ipbus_ctrlreg

Instantiation

slave0 [2/5]

slave0 ipbus_ctrlreg

Instantiation

slave0 [3/5]

slave0 ipbus_ctrlreg

Instantiation

slave0 [4/5]

slave0 ipbus_ctrlreg

Instantiation

slave0 [5/5]

slave0 ipbus_ctrlreg

Instantiation

slave1 [1/4]

slave1 ipbus_reg

Instantiation

slave1 [2/4]

slave1 ipbus_reg

Instantiation

slave1 [3/4]

slave1 ipbus_reg

Instantiation

slave1 [4/4]

slave1 ipbus_reg

Instantiation

slave2 [1/4]

slave2 ipbus_ram

Instantiation

slave2 [2/4]

slave2 ipbus_ram

Instantiation

slave2 [3/4]

slave2 ipbus_ram

Instantiation

slave2 [4/4]

slave2 ipbus_ram

Instantiation

slave3 [1/4]

slave3 ipbus_ctrlreg

Instantiation

slave3 [2/4]

slave3 ipbus_ctrlreg

Instantiation

slave3 [3/4]

slave3 ipbus_ctrlreg

Instantiation

slave3 [4/4]

slave3 ipbus_ctrlreg

Instantiation

slave4 [1/3]

slave4 ipbus_peephole_ram

Instantiation

slave4 [2/3]

slave4 ipbus_peephole_ram

Instantiation

slave4 [3/3]

slave4 ipbus_peephole_ram

Instantiation

slave5 [1/4]

slave5 ipbus_pkt_ctr

Instantiation

slave5 [2/4]

slave5 ipbus_pkt_ctr

Instantiation

slave5 [3/4]

slave5 ipbus_pkt_ctr

Instantiation

slave5 [4/4]

slave5 ipbus_peephole_ram

Instantiation

slave6

slave6 ipbus_pkt_ctr

Instantiation

spi_flash [1/3]

spi_flash ipbus_spi32

Instantiation

spi_flash [2/3]

spi_flash ipbus_spi32

Instantiation

spi_flash [3/3]

spi_flash ipbus_spi32

Instantiation

spi_pll

spi_pll ipbus_spi32

Instantiation

sync_frame

sync_frame std_logic

Signal

sync_frame_i

sync_frame_i std_logic

Signal

tob_spin

tob_spin std_logic

Signal

tob_sync

tob_sync std_logic

Signal

trigger

trigger std_logic_vector ( 31 downto 0 )

Signal

ttc

ttc ipbus_ctrlreg_v

Instantiation

ttc_info

ttc_info ipbus_ttcinfo

Instantiation

ttc_info_delay

ttc_info_delay std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )

Signal

ttc_mgt

ttc_mgt ttc_mgt_channel_status

Signal

ttc_mgt_rx_ok

ttc_mgt_rx_ok std_logic := ' 1 '

Signal

ttc_spin

ttc_spin std_logic

Signal

ttc_status_array

ttc_status_array ipb_reg_v ( 3 downto 0 )

Signal

ttc_sync

ttc_sync std_logic

Signal

ttob_data

ttob_data AlgoOutput

Signal

ttob_output_sink

ttob_output_sink ipbus_tob_sink

Instantiation

tx_bufs [1/2]

tx_bufs ipbus_mgt_source

Instantiation

tx_bufs [2/2]

tx_bufs ipbus_mgt_source

Instantiation

xcvr_control [1/2]

xcvr_control ipbus_dss_xcvr_control

Instantiation

xcvr_control [2/2]

xcvr_control ipbus_con_xcvr_control

Instantiation

xcvr_ctrl_reg

xcvr_ctrl_reg ipb_reg_v ( 1 downto 0 )

Signal

xcvr_status [1/2]

xcvr_status ipb_reg_v ( 7 downto 0 )

Signal

xcvr_status [2/2]

xcvr_status ipb_reg_v ( 1 downto 0 )

Signal

---

The documentation for this class was generated from the following files:

• components/ipbus_util/firmware/hdl/slaves.vhd
• FTM/Control/hdl/slaves_FTM_control.vhd
• FTM/DSS/hdl/slaves_dss.vhd
• FTM/DSS_Algo/hdl/slaves_dss_algo.vhd