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My Project
v0.0.16
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Entities | |
| rtl | architecture |
Libraries | |
| IEEE | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| ipbus | Package <ipbus> |
| spi | Package <spi> |
| ipbus_reg_types | Package <ipbus_reg_types> |
Generics | |
| BYTE_SPI | boolean := FALSE |
| ADDR_WIDTH | natural |
Ports | |
| ipbus_clk | in std_logic |
| reset | in std_logic |
| ipb_in | in ipb_wbus |
| ipb_out | out ipb_rbus |
| spi_in | in spi_mi |
| spi_out | out spi_mo |
| selreg | out std_logic_vector ( 1 downto 0 ) |
Attributes | |
| keep_hierarchy | string |
| keep_hierarchy | ipbus_spi32 : entity is " yes " |
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1.8.13