My Project  v0.0.16
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ipbus_spi32 Entity Reference
Inheritance diagram for ipbus_spi32:
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Collaboration diagram for ipbus_spi32:
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Entities

rtl  architecture
 

Libraries

IEEE 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
ipbus  Package <ipbus>
spi  Package <spi>
ipbus_reg_types  Package <ipbus_reg_types>

Generics

BYTE_SPI  boolean := FALSE
ADDR_WIDTH  natural

Ports

ipbus_clk   in std_logic
reset   in std_logic
ipb_in   in ipb_wbus
ipb_out   out ipb_rbus
spi_in   in spi_mi
spi_out   out spi_mo
selreg   out std_logic_vector ( 1 downto 0 )

Attributes

keep_hierarchy  string
keep_hierarchy  ipbus_spi32 : entity is " yes "

Member Data Documentation

◆ ADDR_WIDTH

ADDR_WIDTH natural
Generic

◆ BYTE_SPI

BYTE_SPI boolean := FALSE
Generic

◆ IEEE

IEEE
Library

◆ ipb_in

ipb_in in ipb_wbus
Port

◆ ipb_out

ipb_out out ipb_rbus
Port

◆ ipbus

ipbus
Package

◆ ipbus_clk

ipbus_clk in std_logic
Port

◆ ipbus_reg_types

ipbus_reg_types
Package

◆ keep_hierarchy [1/2]

keep_hierarchy string
Attribute

◆ keep_hierarchy [2/2]

keep_hierarchy ipbus_spi32 : entity is " yes "
Attribute

◆ reset

reset in std_logic
Port

◆ selreg

selreg out std_logic_vector ( 1 downto 0 )
Port

◆ spi

spi
Package

◆ spi_in

spi_in in spi_mi
Port

◆ spi_out

spi_out out spi_mo
Port

◆ std_logic_1164

std_logic_1164
Package

◆ std_logic_arith

std_logic_arith
Package

◆ std_logic_unsigned


The documentation for this class was generated from the following file: