rtl Architecture Reference

Processes
clock_div	( reset , ipbus_clk )

Constants
DIV_BITS	natural := 2
NSLV	positive := 4

Signals
ram_ptr	std_logic_vector ( ADDR_WIDTH - 3 downto 0 )
ram_write	std_logic
outgoing_data	std_logic_vector ( 31 downto 0 )
incoming_data	std_logic_vector ( 31 downto 0 )
spi_clk	std_logic := ' 0 '
clk_en	std_logic := ' 0 '
ipbw	ipb_wbus_array ( NSLV - 1 downto 0 )
ipbr	ipb_rbus_array ( NSLV - 1 downto 0 )
ipbr_d	ipb_rbus_array ( NSLV - 1 downto 0 )
spi_ctrl	ipb_reg_v ( 3 downto 0 )
spi_stat	ipb_reg_v ( 0 downto 0 )
transfer_count	std_logic_vector ( ADDR_WIDTH downto 0 )
do_spi	std_logic
run_spi	std_logic
busy	std_logic

Instantiations
block_decode	ipbus_fabric_branch <Entity ipbus_fabric_branch>
spi_control	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
arbitration	ipbus_watchdog <Entity ipbus_watchdog>
spi_dpram_out	ipbus_dpram <Entity ipbus_dpram>
spi_dpram_in	ipbus_dpram <Entity ipbus_dpram>
synch	command_sync <Entity command_sync>
spi_engine	spi32_8_control <Entity spi32_8_control>
gen_clock	clock_pulse <Entity clock_pulse>

Member Function Documentation

clock_div()

clock_div	(		reset,
			ipbus_clk
	)

Member Data Documentation

arbitration

arbitration ipbus_watchdog

Instantiation

block_decode

block_decode ipbus_fabric_branch

Instantiation

busy

busy std_logic

Signal

clk_en

clk_en std_logic := ' 0 '

Signal

DIV_BITS

DIV_BITS natural := 2

Constant

do_spi

do_spi std_logic

Signal

gen_clock

gen_clock clock_pulse

Instantiation

incoming_data

incoming_data std_logic_vector ( 31 downto 0 )

Signal

ipbr

ipbr ipb_rbus_array ( NSLV - 1 downto 0 )

Signal

ipbr_d

ipbr_d ipb_rbus_array ( NSLV - 1 downto 0 )

Signal

ipbw

ipbw ipb_wbus_array ( NSLV - 1 downto 0 )

Signal

NSLV

NSLV positive := 4

Constant

outgoing_data

outgoing_data std_logic_vector ( 31 downto 0 )

Signal

ram_ptr

ram_ptr std_logic_vector ( ADDR_WIDTH - 3 downto 0 )

Signal

ram_write

ram_write std_logic

Signal

run_spi

run_spi std_logic

Signal

spi_clk

spi_clk std_logic := ' 0 '

Signal

spi_control

spi_control ipbus_ctrlreg_v

Instantiation

spi_ctrl

spi_ctrl ipb_reg_v ( 3 downto 0 )

Signal

spi_dpram_in

spi_dpram_in ipbus_dpram

Instantiation

spi_dpram_out

spi_dpram_out ipbus_dpram

Instantiation

spi_engine

spi_engine spi32_8_control

Instantiation

spi_stat

spi_stat ipb_reg_v ( 0 downto 0 )

Signal

synch

synch command_sync

Instantiation

transfer_count

transfer_count std_logic_vector ( ADDR_WIDTH downto 0 )

Signal

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The documentation for this class was generated from the following file:

• common/IPbus_SPI/hdl/ipbus_spi32.vhd