spi32_8_control Entity Reference

Inheritance diagram for spi32_8_control:

Entities
rtl	architecture

Libraries
IEEE

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Generics
ADDR_WIDTH	natural
BYTE_SPI	boolean := FALSE

Ports
spi_clk	in std_logic
reset	in std_logic
outgoing_data	in std_logic_vector ( 31 downto 0 )
incoming_data	out std_logic_vector ( 31 downto 0 )
run_spi	in std_logic
busy	out std_logic := ' 0 '
transfer_count	in std_logic_vector ( ADDR_WIDTH + 1 downto 0 )
ram_ptr	out std_logic_vector ( ADDR_WIDTH - 2 downto 0 )
ram_write	out std_logic := ' 0 '
clk_en	out std_logic := ' 0 '
cs_n	out std_logic := ' 1 '
mosi	out std_logic := ' 0 '
miso	in std_logic := ' 0 '

Member Data Documentation

ADDR_WIDTH

ADDR_WIDTH natural

Generic

busy

busy out std_logic := ' 0 '

Port

BYTE_SPI

BYTE_SPI boolean := FALSE

Generic

clk_en

clk_en out std_logic := ' 0 '

Port

cs_n

cs_n out std_logic := ' 1 '

Port

IEEE

IEEE

Library

incoming_data

incoming_data out std_logic_vector ( 31 downto 0 )

Port

miso

miso in std_logic := ' 0 '

Port

mosi

mosi out std_logic := ' 0 '

Port

outgoing_data

outgoing_data in std_logic_vector ( 31 downto 0 )

Port

ram_ptr

ram_ptr out std_logic_vector ( ADDR_WIDTH - 2 downto 0 )

Port

ram_write

ram_write out std_logic := ' 0 '

Port

reset

reset in std_logic

Port

run_spi

run_spi in std_logic

Port

spi_clk

spi_clk in std_logic

Port

std_logic_1164

std_logic_1164

Package

std_logic_arith

std_logic_arith

Package

std_logic_unsigned

std_logic_unsigned

Package

transfer_count

transfer_count in std_logic_vector ( ADDR_WIDTH + 1 downto 0 )

Port

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The documentation for this class was generated from the following file:

• common/IPbus_SPI/hdl/spi32_8_control.vhd