rtl Architecture Reference

Processes
spi_sequencer	( spi_clk , reset , sequencer , run_spi , shift_count )
serdes	( spi_clk , shift_register )
chip_enable	( spi_clk , shift_register )
chip_enable	( spi_clk , shift_register )

Constants
MSB_FIRST	boolean := BYTE_SPI
BIG_FRAME	boolean := BYTE_SPI
TRAP_CODE	boolean := not BYTE_SPI
otp_code	std_logic_vector ( 31 downto 0 ) := x " 0000A03F "

Types
shiftstate	( idle , start_frame , read_mem , shift_io , write_mem , end_frame )

Signals
sequencer	shiftstate := idle
shift_count	integer range 0 to 32 := 0
shift_register	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
mosi_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
miso_rising	std_logic
le_int	std_logic := ' 0 '
ram_index_u	unsigned ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
num_words	std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
num_32words	unsigned ( ADDR_WIDTH - 1 downto 0 )
ram_index_slv	std_logic_vector ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
term_le	std_logic := ' 0 '

Attributes
dont_touch	string
dont_touch	ram_index_u : signal is " true "
dont_touch	num_32words : signal is " true "

Aliases
rem_bytes	is transfer_count ( 1 downto 0 )

Member Function Documentation

chip_enable() [1/2]

chip_enable (   spi_clk ,   shift_register   )

Process

chip_enable() [2/2]

chip_enable (   spi_clk ,   shift_register   )

Process

serdes()

serdes (   spi_clk ,   shift_register   )

Process

spi_sequencer()

spi_sequencer (   spi_clk ,   reset ,   sequencer ,   run_spi ,   shift_count   )

Process

Member Data Documentation

BIG_FRAME

BIG_FRAME boolean := BYTE_SPI

Constant

dont_touch [1/3]

dont_touch string

Attribute

dont_touch [2/3]

dont_touch ram_index_u : signal is " true "

Attribute

dont_touch [3/3]

dont_touch num_32words : signal is " true "

Attribute

le_int

le_int std_logic := ' 0 '

Signal

miso_rising

miso_rising std_logic

Signal

mosi_data

mosi_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

MSB_FIRST

MSB_FIRST boolean := BYTE_SPI

Constant

num_32words

num_32words unsigned ( ADDR_WIDTH - 1 downto 0 )

Signal

num_words

num_words std_logic_vector ( ADDR_WIDTH - 1 downto 0 )

Signal

otp_code

otp_code std_logic_vector ( 31 downto 0 ) := x " 0000A03F "

Constant

ram_index_slv

ram_index_slv std_logic_vector ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

ram_index_u

ram_index_u unsigned ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

rem_bytes

rem_bytes is transfer_count ( 1 downto 0 )

Alias

sequencer

sequencer shiftstate := idle

Signal

shift_count

shift_count integer range 0 to 32 := 0

Signal

shift_register

shift_register std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

shiftstate

shiftstate ( idle , start_frame , read_mem , shift_io , write_mem , end_frame )

Type

term_le

term_le std_logic := ' 0 '

Signal

TRAP_CODE

TRAP_CODE boolean := not BYTE_SPI

Constant

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The documentation for this class was generated from the following file:

• common/IPbus_SPI/hdl/spi32_8_control.vhd