My Project  v0.0.16
Ports | Libraries | Use Clauses
ipbus_ttcinfo Entity Reference
Inheritance diagram for ipbus_ttcinfo:
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Collaboration diagram for ipbus_ttcinfo:
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Entities

rtl  architecture
 

Libraries

IEEE 
UNISIM 

Use Clauses

STD_LOGIC_1164 
numeric_std 
vcomponents 
ipbus  Package <ipbus>
ipbus_reg_types  Package <ipbus_reg_types>
ftm  Package <ftm>

Ports

ipb_clk   in std_logic
ipb_rst   in std_logic
ipb_in   in ipb_wbus
ipb_out   out ipb_rbus
ttc_clk   in std_logic
sync_frame   in std_logic
ttcinfo_clko   in std_logic
ttcinfo_data   out mgt_data
L1A_tx   in std_logic := ' 0 '
BCR_tx   in std_logic := ' 0 '
ECR_tx   in std_logic := ' 0 '
tx_shelf_num   in std_logic_vector ( 3 downto 0 )
ttcinfo_sink_clko   in std_logic
ttcinfo_sink_data   in mgt_data
L1A_rx   out std_logic
BCR_rx   out std_logic
ECR_rx   out std_logic

Member Data Documentation

◆ BCR_rx

BCR_rx out std_logic
Port

◆ BCR_tx

BCR_tx in std_logic := ' 0 '
Port

◆ ECR_rx

ECR_rx out std_logic
Port

◆ ECR_tx

ECR_tx in std_logic := ' 0 '
Port

◆ ftm

ftm
Package

◆ IEEE

IEEE
Library

◆ ipb_clk

ipb_clk in std_logic
Port

◆ ipb_in

ipb_in in ipb_wbus
Port

◆ ipb_out

ipb_out out ipb_rbus
Port

◆ ipb_rst

ipb_rst in std_logic
Port

◆ ipbus

ipbus
Package

◆ ipbus_reg_types

ipbus_reg_types
Package

◆ L1A_rx

L1A_rx out std_logic
Port

◆ L1A_tx

L1A_tx in std_logic := ' 0 '
Port

◆ numeric_std

numeric_std
Package

◆ STD_LOGIC_1164

STD_LOGIC_1164
Package

◆ sync_frame

sync_frame in std_logic
Port

◆ ttc_clk

ttc_clk in std_logic
Port

◆ ttcinfo_clko

ttcinfo_clko in std_logic
Port

◆ ttcinfo_data

◆ ttcinfo_sink_clko

ttcinfo_sink_clko in std_logic
Port

◆ ttcinfo_sink_data

◆ tx_shelf_num

tx_shelf_num in std_logic_vector ( 3 downto 0 )
Port

◆ UNISIM

UNISIM
Library

◆ vcomponents

vcomponents
Package

The documentation for this class was generated from the following file: