rtl Architecture Reference

Processes
retime_ecr	( ttc_clk , tx_ecr_pulse )
retime_ecrid_reset	( ttc_clk , ecrid_reset )
count_error	( ttc_clk , crc_error_count , clear_error , clear_counter )

Signals
ctrl_reg	ipb_reg_v ( 1 downto 0 )
module_status	ipb_reg_v ( 0 downto 0 )
crc_error	std_logic
clear_error	std_logic
clear_counter	std_logic
crc_error_count	natural := 0
crc_error_count_slv	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ttc_tune	std_logic_vector ( 4 downto 0 )
tx_ecr_pulse	std_logic := ' 0 '
tx_ecr	std_logic := ' 0 '
ecr_pulse_d	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ecrid_reset	std_logic := ' 0 '
ecrid_reset_d	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ecrid_reset_pulse	std_logic := ' 0 '
l1id_info	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ttc_info_delay	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
ECR_tx_i	std_logic := ' 0 '
L1A_delayed	std_logic := ' 0 '
BCR_delayed	std_logic := ' 0 '
ECR_delayed	std_logic := ' 0 '

Instantiations
control	ipbus_ttcinfo_control <Entity ipbus_ttcinfo_control>
l1a_pipe	delay_128 <Entity delay_128>
bcr_pipe	delay_128 <Entity delay_128>
ecr_pipe	delay_128 <Entity delay_128>
ttcout	ttcinfo_source <Entity ttcinfo_source>
ttcin	ttcinfo_sink <Entity ttcinfo_sink>

Member Function Documentation

count_error()

count_error	(		ttc_clk,
			crc_error_count,
			clear_error,
			clear_counter
	)

retime_ecr()

retime_ecr	(		ttc_clk,
			tx_ecr_pulse
	)

retime_ecrid_reset()

retime_ecrid_reset (   ttc_clk ,   ecrid_reset   )

Process

Member Data Documentation

BCR_delayed

BCR_delayed std_logic := ' 0 '

Signal

bcr_pipe

bcr_pipe delay_128

Instantiation

clear_counter

clear_counter std_logic

Signal

clear_error

clear_error std_logic

Signal

control

control ipbus_ttcinfo_control

Instantiation

crc_error

crc_error std_logic

Signal

crc_error_count

crc_error_count natural := 0

Signal

crc_error_count_slv

crc_error_count_slv std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

ctrl_reg

ctrl_reg ipb_reg_v ( 1 downto 0 )

Signal

ECR_delayed

ECR_delayed std_logic := ' 0 '

Signal

ecr_pipe

ecr_pipe delay_128

Instantiation

ecr_pulse_d

ecr_pulse_d std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

ECR_tx_i

ECR_tx_i std_logic := ' 0 '

Signal

ecrid_reset

ecrid_reset std_logic := ' 0 '

Signal

ecrid_reset_d

ecrid_reset_d std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

ecrid_reset_pulse

ecrid_reset_pulse std_logic := ' 0 '

Signal

L1A_delayed

L1A_delayed std_logic := ' 0 '

Signal

l1a_pipe

l1a_pipe delay_128

Instantiation

l1id_info

l1id_info std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

module_status

module_status ipb_reg_v ( 0 downto 0 )

Signal

ttc_info_delay

ttc_info_delay std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )

Signal

ttc_tune

ttc_tune std_logic_vector ( 4 downto 0 )

Signal

ttcin

ttcin ttcinfo_sink

Instantiation

ttcout

ttcout ttcinfo_source

Instantiation

tx_ecr

tx_ecr std_logic := ' 0 '

Signal

tx_ecr_pulse

tx_ecr_pulse std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/ipbus_ttcinfo.vhd