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My Project
v0.0.16
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| rtl | architecture |
Libraries | |
| IEEE | |
| UNISIM | |
Use Clauses | |
| STD_LOGIC_1164 | |
| numeric_std | |
| vcomponents | |
| ftm | Package <ftm> |
Ports | |
| data_clk | in std_logic |
| data_in | in mgt_data |
| ttc_clk | in std_logic |
| crc_ignore | in std_logic |
| mgt_rx_ok | in std_logic := ' 1 ' |
| ttc_tune | in std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' ) |
| L1A | out std_logic |
| BCR | out std_logic |
| ECR | out std_logic |
| crc_error | out std_logic := ' 0 ' |
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1.8.13