rtl Architecture Reference

Processes
capture_data	( data_clk , data_in )
word_align	( data_clk , comma_det , word_index )
delay_stuff	( data_clk , comma_det , data_int )
check_crc	( word_index , crc9 )
grab_n_gate	( data_clk , data_int , word_index , bits_valid )

Constants
NUM_WORDS	natural := 4
REVERSE_BIT_ORDER	boolean := TRUE

Signals
ttcinfo	mgt_data_array ( 3 downto 0 )
ttcreg	mgt_data_array ( 3 downto 0 )
crc_start	std_logic := ' 0 '
crc9	std_logic_vector ( 8 downto 0 )
rx_crc	std_logic_vector ( 8 downto 0 )
data_int	mgt_data
comma_det	std_logic
crc_in	std_logic_vector ( 31 downto 0 )
crc_ok	std_logic := ' 1 '
bits_valid	std_logic := ' 1 '
word_index	natural range 0 to NUM_WORDS - 1 := 0
ttc_bits	std_logic_vector ( 18 downto 16 ) := ( others = > ' 0 ' )
ttc_int	std_logic_vector ( 18 downto 16 ) := ( others = > ' 0 ' )
ttc_bits_out	std_logic_vector ( 18 downto 16 ) := ( others = > ' 0 ' )

Instantiations
crc32	osum_crc9d32 <Entity osum_crc9d32>
then_delay	srlc32e

Member Function Documentation

capture_data()

capture_data (   data_clk ,   data_in   )

Process

check_crc()

check_crc	(		word_index,
			crc9
	)

delay_stuff()

delay_stuff (   data_clk ,   comma_det ,   data_int   )

Process

grab_n_gate()

grab_n_gate (   data_clk ,   data_int ,   word_index ,   bits_valid   )

Process

word_align()

word_align (   data_clk ,   comma_det ,   word_index   )

Process

Member Data Documentation

bits_valid

bits_valid std_logic := ' 1 '

Signal

comma_det

comma_det std_logic

Signal

crc32

crc32 osum_crc9d32

Instantiation

crc9

crc9 std_logic_vector ( 8 downto 0 )

Signal

crc_in

crc_in std_logic_vector ( 31 downto 0 )

Signal

crc_ok

crc_ok std_logic := ' 1 '

Signal

crc_start

crc_start std_logic := ' 0 '

Signal

data_int

data_int mgt_data

Signal

NUM_WORDS

NUM_WORDS natural := 4

Constant

REVERSE_BIT_ORDER

REVERSE_BIT_ORDER boolean := TRUE

Constant

rx_crc

rx_crc std_logic_vector ( 8 downto 0 )

Signal

then_delay

then_delay srlc32e

Instantiation

ttc_bits

ttc_bits std_logic_vector ( 18 downto 16 ) := ( others = > ' 0 ' )

Signal

ttc_bits_out

ttc_bits_out std_logic_vector ( 18 downto 16 ) := ( others = > ' 0 ' )

Signal

ttc_int

ttc_int std_logic_vector ( 18 downto 16 ) := ( others = > ' 0 ' )

Signal

ttcinfo

ttcinfo mgt_data_array ( 3 downto 0 )

Signal

ttcreg

ttcreg mgt_data_array ( 3 downto 0 )

Signal

word_index

word_index natural range 0 to NUM_WORDS - 1 := 0

Signal

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/ttcinfo_sink.vhd