testbench Architecture Reference

Processes
ipbus_stim	( )
ttcinfo_error_stim	( )
mgt_status_stim	( )
mgt_stim	( )
ipbus_stim	( )
ipbus_stim	( )

Procedures
	ipbus_cycle( )
	ipbus_null( )
	ipbus_write( )
	ipbus_read( )
	ipbus_cycle( )
	ipbus_write( )
	ipbus_read( )
	ipbus_cycle( )
	ipbus_null( )
	ipbus_write( )
	ipbus_read( )

Constants
ipbus_period	time := 32 ns
dclk_period	time := 20 ns
WORDSPERFRAME	positive := 4
drp_period	time := 8 ns
ttc_period	time := 25 . 0 ns
mgt_halfperiod	time := ttc_period / ( WORDSPERFRAME * 2 )
bc_halfperiod	time := mgt_halfperiod * WORDSPERFRAME
bc_period	time := bc_halfperiod * 2
N_TXS	positive := 8
N_RXS	positive := 8
mgt_clk_period	time := 4 ns

Signals
reset	STD_LOGIC := ' 1 '
ipbus_clk	STD_LOGIC := ' 0 '
ipbus_int	ipb_wbus := IPB_WBUS_NULL
ipbus_out	ipb_rbus
dclk	STD_LOGIC := ' 0 '
BC_clock	std_logic := ' 0 '
mgt_clk	std_logic := ' 0 '
drp_clk	std_logic := ' 0 '
hw_addr	std_logic_vector ( 4 downto 0 ) := " 00001 "
flash_spi_in	spi_mi
flash_spi_out	spi_mo
mgt_source_clk2	std_logic_vector ( N_TXS - 1 downto 0 )
mgt_source_data	mgt_data_array ( N_TXS - 1 downto 0 )
mgt_sink_clk2	std_logic_vector ( N_RXS - 1 downto 0 )
mgt_sink_data	mgt_data_array ( N_RXS - 1 downto 0 )
ttcinfo_sink_data	mgt_data
ttcinfo_source_data	mgt_data
ttcinfo_link_errors	mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
data	std_logic_vector ( 31 downto 0 )
ctrl	std_logic_vector ( 3 downto 0 )
rxdata	std_logic_vector ( 31 downto 0 )
rxctrl	std_logic_vector ( 3 downto 0 )
mgt_status	mgt_status_bundle
hw_addr	std_logic_vector ( 4 downto 0 )
pll_spi_in	spi_mi
pll_lock	std_logic_vector ( 3 downto 0 )
spin_dss	std_logic
sync_dss	std_logic

Instantiations
uut	ipbus_xadc_array <Entity ipbus_xadc_array>
uut	slaves <Entity slaves>
uut	slaves <Entity slaves>

Member Function Documentation

ipbus_cycle() [1/3]

ipbus_cycle

(

)

ipbus_cycle() [2/3]

ipbus_cycle

(

)

ipbus_cycle() [3/3]

ipbus_cycle ( )

Procedure

ipbus_null() [1/2]

ipbus_null ( )

Procedure

ipbus_null() [2/2]

ipbus_null ( )

Procedure

ipbus_read() [1/3]

ipbus_read ( )

Procedure

ipbus_read() [2/3]

ipbus_read ( )

Procedure

ipbus_read() [3/3]

ipbus_read ( )

Procedure

ipbus_stim() [1/3]

ipbus_stim ( )

Process

ipbus_stim() [2/3]

ipbus_stim ( )

Process

ipbus_stim() [3/3]

ipbus_stim ( )

Process

ipbus_write() [1/3]

ipbus_write ( )

Procedure

ipbus_write() [2/3]

ipbus_write ( )

Procedure

ipbus_write() [3/3]

ipbus_write ( )

Procedure

mgt_status_stim()

mgt_status_stim ( )

Process

mgt_stim()

mgt_stim ( )

Process

ttcinfo_error_stim()

ttcinfo_error_stim

(

)

Member Data Documentation

BC_clock

BC_clock std_logic := ' 0 '

Signal

bc_halfperiod

bc_halfperiod time := mgt_halfperiod * WORDSPERFRAME

Constant

bc_period

bc_period time := bc_halfperiod * 2

Constant

ctrl

ctrl std_logic_vector ( 3 downto 0 )

Signal

data

data std_logic_vector ( 31 downto 0 )

Signal

dclk

dclk STD_LOGIC := ' 0 '

Signal

dclk_period

dclk_period time := 20 ns

Constant

drp_clk

drp_clk std_logic := ' 0 '

Signal

drp_period

drp_period time := 8 ns

Constant

flash_spi_in

flash_spi_in spi_mi

Signal

flash_spi_out

flash_spi_out spi_mo

Signal

hw_addr [1/2]

hw_addr std_logic_vector ( 4 downto 0 )

Signal

hw_addr [2/2]

hw_addr std_logic_vector ( 4 downto 0 ) := " 00001 "

Signal

ipbus_clk

ipbus_clk STD_LOGIC := ' 0 '

Signal

ipbus_int

ipbus_int ipb_wbus := IPB_WBUS_NULL

Signal

ipbus_out

ipbus_out ipb_rbus

Signal

ipbus_period

ipbus_period time := 32 ns

Constant

mgt_clk

mgt_clk std_logic := ' 0 '

Signal

mgt_clk_period

mgt_clk_period time := 4 ns

Constant

mgt_halfperiod

mgt_halfperiod time := ttc_period / ( WORDSPERFRAME * 2 )

Constant

mgt_sink_clk2

mgt_sink_clk2 std_logic_vector ( N_RXS - 1 downto 0 )

Signal

mgt_sink_data

mgt_sink_data mgt_data_array ( N_RXS - 1 downto 0 )

Signal

mgt_source_clk2

mgt_source_clk2 std_logic_vector ( N_TXS - 1 downto 0 )

Signal

mgt_source_data

mgt_source_data mgt_data_array ( N_TXS - 1 downto 0 )

Signal

mgt_status

mgt_status mgt_status_bundle

Signal

N_RXS

N_RXS positive := 8

Constant

N_TXS

N_TXS positive := 8

Constant

pll_lock

pll_lock std_logic_vector ( 3 downto 0 )

Signal

pll_spi_in

pll_spi_in spi_mi

Signal

reset

reset STD_LOGIC := ' 1 '

Signal

rxctrl

rxctrl std_logic_vector ( 3 downto 0 )

Signal

rxdata

rxdata std_logic_vector ( 31 downto 0 )

Signal

spin_dss

spin_dss std_logic

Signal

sync_dss

sync_dss std_logic

Signal

ttc_period

ttc_period time := 25 . 0 ns

Constant

ttcinfo_link_errors

ttcinfo_link_errors mgt_data := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )

Signal

ttcinfo_sink_data

ttcinfo_sink_data mgt_data

Signal

ttcinfo_source_data

ttcinfo_source_data mgt_data

Signal

uut [1/3]

uut ipbus_xadc_array

Instantiation

uut [2/3]

uut slaves

Instantiation

uut [3/3]

uut slaves

Instantiation

WORDSPERFRAME

WORDSPERFRAME positive := 4

Constant

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The documentation for this class was generated from the following files:

• common/xadc/sim/IPBus_slave_tb.vhd
• testbench/IPBus_slave_buffersync_tb.vhd