L1A_Gen Entity Reference

Inheritance diagram for L1A_Gen:

Entities
rtl	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
numeric_std

Generics
ADDR_WIDTH	natural := 8

Ports
clock	in STD_LOGIC
reset	in STD_LOGIC
run_L1A	in STD_LOGIC
num_L1A	in std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
delay	in std_logic_vector ( 31 downto 0 )
index_addr	out std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
busy	out std_logic
repeat	in std_logic
bcrst	in std_logic
nowait	in std_logic
L1A	out STD_LOGIC := ' 0 '

Member Data Documentation

ADDR_WIDTH

ADDR_WIDTH natural := 8

Generic

bcrst

bcrst in std_logic

Port

busy

busy out std_logic

Port

clock

clock in STD_LOGIC

Port

delay

delay in std_logic_vector ( 31 downto 0 )

Port

IEEE

IEEE

Library

index_addr

index_addr out std_logic_vector ( ADDR_WIDTH - 1 downto 0 )

Port

L1A

L1A out STD_LOGIC := ' 0 '

Port

nowait

nowait in std_logic

Port

num_L1A

num_L1A in std_logic_vector ( ADDR_WIDTH - 1 downto 0 )

Port

numeric_std

numeric_std

Package

repeat

repeat in std_logic

Port

reset

reset in STD_LOGIC

Port

run_L1A

run_L1A in STD_LOGIC

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/L1A_Gen.vhd