behavior Architecture Reference

Processes
stim_proc	( )

Constants
CONTROL_CLK_period	time := 10 ns

Signals
CPLD_CLK	std_logic := ' 0 '
CONTROL_CSn	std_logic := ' 0 '
CONTROL_ENAB	std_logic := ' 0 '
CONTROL_MOSI	std_logic := ' 0 '
CONTROL_CLK	std_logic := ' 0 '
CONTROL_ADR	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
CABLE_PRESENT_n	std_logic := ' 0 '
CABLE_CLK	std_logic := ' 0 '
CABLE_MOSI	std_logic := ' 0 '
CABLE_CSn	std_logic := ' 0 '
CABLE_ADR	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
PLL_SPI_MISO	std_logic := ' 0 '
CONTROL_MISO	std_logic
CABLE_MISO	std_logic
PLL_SPI_CLK	std_logic
PLL_SPI_MOSI	std_logic
PLL_SPI_LE	std_logic_vector ( 3 downto 0 )

Instantiations
uut	PLL_SPI <Entity PLL_SPI>

Member Function Documentation

stim_proc()

stim_proc

(

)

Member Data Documentation

CABLE_ADR

CABLE_ADR std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

CABLE_CLK

CABLE_CLK std_logic := ' 0 '

Signal

CABLE_CSn

CABLE_CSn std_logic := ' 0 '

Signal

CABLE_MISO

CABLE_MISO std_logic

Signal

CABLE_MOSI

CABLE_MOSI std_logic := ' 0 '

Signal

CABLE_PRESENT_n

CABLE_PRESENT_n std_logic := ' 0 '

Signal

CONTROL_ADR

CONTROL_ADR std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

CONTROL_CLK

CONTROL_CLK std_logic := ' 0 '

Signal

CONTROL_CLK_period

CONTROL_CLK_period time := 10 ns

Constant

CONTROL_CSn

CONTROL_CSn std_logic := ' 0 '

Signal

CONTROL_ENAB

CONTROL_ENAB std_logic := ' 0 '

Signal

CONTROL_MISO

CONTROL_MISO std_logic

Signal

CONTROL_MOSI

CONTROL_MOSI std_logic := ' 0 '

Signal

CPLD_CLK

CPLD_CLK std_logic := ' 0 '

Signal

PLL_SPI_CLK

PLL_SPI_CLK std_logic

Signal

PLL_SPI_LE

PLL_SPI_LE std_logic_vector ( 3 downto 0 )

Signal

PLL_SPI_MISO

PLL_SPI_MISO std_logic := ' 0 '

Signal

PLL_SPI_MOSI

PLL_SPI_MOSI std_logic

Signal

uut

uut PLL_SPI

Instantiation

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The documentation for this class was generated from the following file:

• FTM/CPLDs/PLL_SPI/PLL_SPI_tb.vhd