ROCKETIO_WRAPPER_GTX_TILE Entity Reference

Inheritance diagram for ROCKETIO_WRAPPER_GTX_TILE:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
TILE_SIM_GTXRESET_SPEEDUP	integer := 0
TILE_SIM_PLL_PERDIV2	bit_vector := x " 0c8 "
TILE_CHAN_BOND_MODE_0	string := " OFF "
TILE_CHAN_BOND_LEVEL_0	integer := 0
TILE_CHAN_BOND_MODE_1	string := " OFF "
TILE_CHAN_BOND_LEVEL_1	integer := 0

Ports
LOOPBACK0_IN	in std_logic_vector ( 2 downto 0 )
LOOPBACK1_IN	in std_logic_vector ( 2 downto 0 )
RXPOWERDOWN0_IN	in std_logic_vector ( 1 downto 0 )
TXPOWERDOWN0_IN	in std_logic_vector ( 1 downto 0 )
RXPOWERDOWN1_IN	in std_logic_vector ( 1 downto 0 )
TXPOWERDOWN1_IN	in std_logic_vector ( 1 downto 0 )
RXCHARISCOMMA0_OUT	out std_logic
RXCHARISK0_OUT	out std_logic
RXDISPERR0_OUT	out std_logic
RXNOTINTABLE0_OUT	out std_logic
RXRUNDISP0_OUT	out std_logic
RXCHARISCOMMA1_OUT	out std_logic
RXCHARISK1_OUT	out std_logic
RXDISPERR1_OUT	out std_logic
RXNOTINTABLE1_OUT	out std_logic
RXRUNDISP1_OUT	out std_logic
RXCLKCORCNT0_OUT	out std_logic_vector ( 2 downto 0 )
RXCLKCORCNT1_OUT	out std_logic_vector ( 2 downto 0 )
RXENMCOMMAALIGN0_IN	in std_logic
RXENMCOMMAALIGN1_IN	in std_logic
RXENPCOMMAALIGN0_IN	in std_logic
RXENPCOMMAALIGN1_IN	in std_logic
RXDATA0_OUT	out std_logic_vector ( 7 downto 0 )
RXDATA1_OUT	out std_logic_vector ( 7 downto 0 )
RXRECCLK0_OUT	out std_logic
RXRECCLK1_OUT	out std_logic
RXRESET0_IN	in std_logic
RXRESET1_IN	in std_logic
RXUSRCLK0_IN	in std_logic
RXUSRCLK1_IN	in std_logic
RXUSRCLK20_IN	in std_logic
RXUSRCLK21_IN	in std_logic
RXELECIDLE0_OUT	out std_logic
RXELECIDLE1_OUT	out std_logic
RXN0_IN	in std_logic
RXN1_IN	in std_logic
RXP0_IN	in std_logic
RXP1_IN	in std_logic
RXBUFRESET0_IN	in std_logic
RXBUFRESET1_IN	in std_logic
RXBUFSTATUS0_OUT	out std_logic_vector ( 2 downto 0 )
RXBUFSTATUS1_OUT	out std_logic_vector ( 2 downto 0 )
CLKIN_IN	in std_logic
GTXRESET_IN	in std_logic
PLLLKDET_OUT	out std_logic
REFCLKOUT_OUT	out std_logic
RESETDONE0_OUT	out std_logic
RESETDONE1_OUT	out std_logic
TXCHARDISPMODE0_IN	in std_logic
TXCHARDISPMODE1_IN	in std_logic
TXCHARDISPVAL0_IN	in std_logic
TXCHARDISPVAL1_IN	in std_logic
TXCHARISK0_IN	in std_logic
TXCHARISK1_IN	in std_logic
TXBUFSTATUS0_OUT	out std_logic_vector ( 1 downto 0 )
TXBUFSTATUS1_OUT	out std_logic_vector ( 1 downto 0 )
TXDATA0_IN	in std_logic_vector ( 7 downto 0 )
TXDATA1_IN	in std_logic_vector ( 7 downto 0 )
TXOUTCLK0_OUT	out std_logic
TXOUTCLK1_OUT	out std_logic
TXRESET0_IN	in std_logic
TXRESET1_IN	in std_logic
TXUSRCLK0_IN	in std_logic
TXUSRCLK1_IN	in std_logic
TXUSRCLK20_IN	in std_logic
TXUSRCLK21_IN	in std_logic
TXN0_OUT	out std_logic
TXN1_OUT	out std_logic
TXP0_OUT	out std_logic
TXP1_OUT	out std_logic
rxpolarity	in std_logic_vector ( 1 downto 0 )
txpolarity	in std_logic_vector ( 1 downto 0 )

Member Data Documentation

CLKIN_IN

CLKIN_IN in std_logic

Port

GTXRESET_IN

GTXRESET_IN in std_logic

Port

ieee

ieee

Library

LOOPBACK0_IN

LOOPBACK0_IN in std_logic_vector ( 2 downto 0 )

Port

LOOPBACK1_IN

LOOPBACK1_IN in std_logic_vector ( 2 downto 0 )

Port

numeric_std

numeric_std

Package

PLLLKDET_OUT

PLLLKDET_OUT out std_logic

Port

REFCLKOUT_OUT

REFCLKOUT_OUT out std_logic

Port

RESETDONE0_OUT

RESETDONE0_OUT out std_logic

Port

RESETDONE1_OUT

RESETDONE1_OUT out std_logic

Port

RXBUFRESET0_IN

RXBUFRESET0_IN in std_logic

Port

RXBUFRESET1_IN

RXBUFRESET1_IN in std_logic

Port

RXBUFSTATUS0_OUT

RXBUFSTATUS0_OUT out std_logic_vector ( 2 downto 0 )

Port

RXBUFSTATUS1_OUT

RXBUFSTATUS1_OUT out std_logic_vector ( 2 downto 0 )

Port

RXCHARISCOMMA0_OUT

RXCHARISCOMMA0_OUT out std_logic

Port

RXCHARISCOMMA1_OUT

RXCHARISCOMMA1_OUT out std_logic

Port

RXCHARISK0_OUT

RXCHARISK0_OUT out std_logic

Port

RXCHARISK1_OUT

RXCHARISK1_OUT out std_logic

Port

RXCLKCORCNT0_OUT

RXCLKCORCNT0_OUT out std_logic_vector ( 2 downto 0 )

Port

RXCLKCORCNT1_OUT

RXCLKCORCNT1_OUT out std_logic_vector ( 2 downto 0 )

Port

RXDATA0_OUT

RXDATA0_OUT out std_logic_vector ( 7 downto 0 )

Port

RXDATA1_OUT

RXDATA1_OUT out std_logic_vector ( 7 downto 0 )

Port

RXDISPERR0_OUT

RXDISPERR0_OUT out std_logic

Port

RXDISPERR1_OUT

RXDISPERR1_OUT out std_logic

Port

RXELECIDLE0_OUT

RXELECIDLE0_OUT out std_logic

Port

RXELECIDLE1_OUT

RXELECIDLE1_OUT out std_logic

Port

RXENMCOMMAALIGN0_IN

RXENMCOMMAALIGN0_IN in std_logic

Port

RXENMCOMMAALIGN1_IN

RXENMCOMMAALIGN1_IN in std_logic

Port

RXENPCOMMAALIGN0_IN

RXENPCOMMAALIGN0_IN in std_logic

Port

RXENPCOMMAALIGN1_IN

RXENPCOMMAALIGN1_IN in std_logic

Port

RXN0_IN

RXN0_IN in std_logic

Port

RXN1_IN

RXN1_IN in std_logic

Port

RXNOTINTABLE0_OUT

RXNOTINTABLE0_OUT out std_logic

Port

RXNOTINTABLE1_OUT

RXNOTINTABLE1_OUT out std_logic

Port

RXP0_IN

RXP0_IN in std_logic

Port

RXP1_IN

RXP1_IN in std_logic

Port

rxpolarity

rxpolarity in std_logic_vector ( 1 downto 0 )

Port

RXPOWERDOWN0_IN

RXPOWERDOWN0_IN in std_logic_vector ( 1 downto 0 )

Port

RXPOWERDOWN1_IN

RXPOWERDOWN1_IN in std_logic_vector ( 1 downto 0 )

Port

RXRECCLK0_OUT

RXRECCLK0_OUT out std_logic

Port

RXRECCLK1_OUT

RXRECCLK1_OUT out std_logic

Port

RXRESET0_IN

RXRESET0_IN in std_logic

Port

RXRESET1_IN

RXRESET1_IN in std_logic

Port

RXRUNDISP0_OUT

RXRUNDISP0_OUT out std_logic

Port

RXRUNDISP1_OUT

RXRUNDISP1_OUT out std_logic

Port

RXUSRCLK0_IN

RXUSRCLK0_IN in std_logic

Port

RXUSRCLK1_IN

RXUSRCLK1_IN in std_logic

Port

RXUSRCLK20_IN

RXUSRCLK20_IN in std_logic

Port

RXUSRCLK21_IN

RXUSRCLK21_IN in std_logic

Port

std_logic_1164

std_logic_1164

Package

TILE_CHAN_BOND_LEVEL_0

TILE_CHAN_BOND_LEVEL_0 integer := 0

Generic

TILE_CHAN_BOND_LEVEL_1

TILE_CHAN_BOND_LEVEL_1 integer := 0

Generic

TILE_CHAN_BOND_MODE_0

TILE_CHAN_BOND_MODE_0 string := " OFF "

Generic

TILE_CHAN_BOND_MODE_1

TILE_CHAN_BOND_MODE_1 string := " OFF "

Generic

TILE_SIM_GTXRESET_SPEEDUP

TILE_SIM_GTXRESET_SPEEDUP integer := 0

Generic

TILE_SIM_PLL_PERDIV2

TILE_SIM_PLL_PERDIV2 bit_vector := x " 0c8 "

Generic

TXBUFSTATUS0_OUT

TXBUFSTATUS0_OUT out std_logic_vector ( 1 downto 0 )

Port

TXBUFSTATUS1_OUT

TXBUFSTATUS1_OUT out std_logic_vector ( 1 downto 0 )

Port

TXCHARDISPMODE0_IN

TXCHARDISPMODE0_IN in std_logic

Port

TXCHARDISPMODE1_IN

TXCHARDISPMODE1_IN in std_logic

Port

TXCHARDISPVAL0_IN

TXCHARDISPVAL0_IN in std_logic

Port

TXCHARDISPVAL1_IN

TXCHARDISPVAL1_IN in std_logic

Port

TXCHARISK0_IN

TXCHARISK0_IN in std_logic

Port

TXCHARISK1_IN

TXCHARISK1_IN in std_logic

Port

TXDATA0_IN

TXDATA0_IN in std_logic_vector ( 7 downto 0 )

Port

TXDATA1_IN

TXDATA1_IN in std_logic_vector ( 7 downto 0 )

Port

TXN0_OUT

TXN0_OUT out std_logic

Port

TXN1_OUT

TXN1_OUT out std_logic

Port

TXOUTCLK0_OUT

TXOUTCLK0_OUT out std_logic

Port

TXOUTCLK1_OUT

TXOUTCLK1_OUT out std_logic

Port

TXP0_OUT

TXP0_OUT out std_logic

Port

TXP1_OUT

TXP1_OUT out std_logic

Port

txpolarity

txpolarity in std_logic_vector ( 1 downto 0 )

Port

TXPOWERDOWN0_IN

TXPOWERDOWN0_IN in std_logic_vector ( 1 downto 0 )

Port

TXPOWERDOWN1_IN

TXPOWERDOWN1_IN in std_logic_vector ( 1 downto 0 )

Port

TXRESET0_IN

TXRESET0_IN in std_logic

Port

TXRESET1_IN

TXRESET1_IN in std_logic

Port

TXUSRCLK0_IN

TXUSRCLK0_IN in std_logic

Port

TXUSRCLK1_IN

TXUSRCLK1_IN in std_logic

Port

TXUSRCLK20_IN

TXUSRCLK20_IN in std_logic

Port

TXUSRCLK21_IN

TXUSRCLK21_IN in std_logic

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx_tile.vhd