RTL Architecture Reference

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
rxdata0_i	std_logic_vector ( 31 downto 0 )
rxchariscomma0_float_i	std_logic_vector ( 2 downto 0 )
rxcharisk0_float_i	std_logic_vector ( 2 downto 0 )
rxdisperr0_float_i	std_logic_vector ( 2 downto 0 )
rxnotintable0_float_i	std_logic_vector ( 2 downto 0 )
rxrundisp0_float_i	std_logic_vector ( 2 downto 0 )
txdata0_i	std_logic_vector ( 31 downto 0 )
rxdata1_i	std_logic_vector ( 31 downto 0 )
rxchariscomma1_float_i	std_logic_vector ( 2 downto 0 )
rxcharisk1_float_i	std_logic_vector ( 2 downto 0 )
rxdisperr1_float_i	std_logic_vector ( 2 downto 0 )
rxnotintable1_float_i	std_logic_vector ( 2 downto 0 )
rxrundisp1_float_i	std_logic_vector ( 2 downto 0 )
txdata1_i	std_logic_vector ( 31 downto 0 )

Instantiations
gtx_dual_i	gtx_dual
gtx_dual_i	gtx_dual

Member Data Documentation

gtx_dual_i [1/2]

gtx_dual_i gtx_dual

Instantiation

gtx_dual_i [2/2]

gtx_dual_i gtx_dual

Instantiation

rxchariscomma0_float_i

rxchariscomma0_float_i std_logic_vector ( 2 downto 0 )

Signal

rxchariscomma1_float_i

rxchariscomma1_float_i std_logic_vector ( 2 downto 0 )

Signal

rxcharisk0_float_i

rxcharisk0_float_i std_logic_vector ( 2 downto 0 )

Signal

rxcharisk1_float_i

rxcharisk1_float_i std_logic_vector ( 2 downto 0 )

Signal

rxdata0_i

rxdata0_i std_logic_vector ( 31 downto 0 )

Signal

rxdata1_i

rxdata1_i std_logic_vector ( 31 downto 0 )

Signal

rxdisperr0_float_i

rxdisperr0_float_i std_logic_vector ( 2 downto 0 )

Signal

rxdisperr1_float_i

rxdisperr1_float_i std_logic_vector ( 2 downto 0 )

Signal

rxnotintable0_float_i

rxnotintable0_float_i std_logic_vector ( 2 downto 0 )

Signal

rxnotintable1_float_i

rxnotintable1_float_i std_logic_vector ( 2 downto 0 )

Signal

rxrundisp0_float_i

rxrundisp0_float_i std_logic_vector ( 2 downto 0 )

Signal

rxrundisp1_float_i

rxrundisp1_float_i std_logic_vector ( 2 downto 0 )

Signal

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_ground_vec_i

tied_to_ground_vec_i std_logic_vector ( 63 downto 0 )

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

txdata0_i

txdata0_i std_logic_vector ( 31 downto 0 )

Signal

txdata1_i

txdata1_i std_logic_vector ( 31 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx_tile.vhd