UDP_if Entity Reference

Inheritance diagram for UDP_if:

Collaboration diagram for UDP_if:

Entities
flat	architecture

Libraries
ieee
ipbus_lib

Use Clauses
std_logic_1164
numeric_std
ipbus	Package <ipbus>

Generics
BUFWIDTH	natural := 2
INTERNALWIDTH	natural := 1
ADDRWIDTH	natural := 11
SECONDARYPORT	std_logic := ' 0 '
IPBUSPORT	std_logic_vector ( 15 DOWNTO 0 ) := x " C351 "

Ports
mac_clk	in std_logic
rst_macclk	in std_logic
ipb_clk	in std_logic
rst_ipb	in std_logic
IP_addr	in std_logic_vector ( 31 DOWNTO 0 )
MAC_addr	in std_logic_vector ( 47 DOWNTO 0 )
ipbus_port	in std_logic_vector ( 15 DOWNTO 0 ) := x " C351 "
enable	in std_logic
RARP	in std_logic
mac_rx_data	in std_logic_vector ( 7 DOWNTO 0 )
mac_rx_error	in std_logic
mac_rx_last	in std_logic
mac_rx_valid	in std_logic
mac_tx_ready	in std_logic
pkt_done_read	in std_logic
pkt_done_write	in std_logic
raddr	in std_logic_vector ( 11 DOWNTO 0 )
waddr	in std_logic_vector ( 11 DOWNTO 0 )
wdata	in std_logic_vector ( 31 DOWNTO 0 )
we	in std_logic
busy	out std_logic
mac_tx_data	out std_logic_vector ( 7 DOWNTO 0 )
mac_tx_error	out std_logic
mac_tx_last	out std_logic
mac_tx_valid	out std_logic
My_IP_addr	out std_logic_vector ( 31 DOWNTO 0 )
Got_IP_addr	out std_logic
pkt_rdy	out std_logic
rdata	out std_logic_vector ( 31 DOWNTO 0 )
rxpacket_ignored	out std_logic
rxpacket_dropped	out std_logic

Member Data Documentation

ADDRWIDTH

ADDRWIDTH natural := 11

Generic

BUFWIDTH

BUFWIDTH natural := 2

Generic

busy

busy out std_logic

Port

enable

enable in std_logic

Port

Got_IP_addr

Got_IP_addr out std_logic

Port

ieee

ieee

Library

INTERNALWIDTH

INTERNALWIDTH natural := 1

Generic

IP_addr

IP_addr in std_logic_vector ( 31 DOWNTO 0 )

Port

ipb_clk

ipb_clk in std_logic

Port

ipbus

ipbus

Package

ipbus_lib

ipbus_lib

Library

ipbus_port

ipbus_port in std_logic_vector ( 15 DOWNTO 0 ) := x " C351 "

Port

IPBUSPORT

IPBUSPORT std_logic_vector ( 15 DOWNTO 0 ) := x " C351 "

Generic

MAC_addr

MAC_addr in std_logic_vector ( 47 DOWNTO 0 )

Port

mac_clk

mac_clk in std_logic

Port

mac_rx_data

mac_rx_data in std_logic_vector ( 7 DOWNTO 0 )

Port

mac_rx_error

mac_rx_error in std_logic

Port

mac_rx_last

mac_rx_last in std_logic

Port

mac_rx_valid

mac_rx_valid in std_logic

Port

mac_tx_data

mac_tx_data out std_logic_vector ( 7 DOWNTO 0 )

Port

mac_tx_error

mac_tx_error out std_logic

Port

mac_tx_last

mac_tx_last out std_logic

Port

mac_tx_ready

mac_tx_ready in std_logic

Port

mac_tx_valid

mac_tx_valid out std_logic

Port

My_IP_addr

My_IP_addr out std_logic_vector ( 31 DOWNTO 0 )

Port

numeric_std

numeric_std

Package

pkt_done_read

pkt_done_read in std_logic

Port

pkt_done_write

pkt_done_write in std_logic

Port

pkt_rdy

pkt_rdy out std_logic

Port

raddr

raddr in std_logic_vector ( 11 DOWNTO 0 )

Port

RARP

RARP in std_logic

Port

rdata

rdata out std_logic_vector ( 31 DOWNTO 0 )

Port

rst_ipb

rst_ipb in std_logic

Port

rst_macclk

rst_macclk in std_logic

Port

rxpacket_dropped

rxpacket_dropped out std_logic

Port

rxpacket_ignored

rxpacket_ignored out std_logic

Port

SECONDARYPORT

SECONDARYPORT std_logic := ' 0 '

Generic

std_logic_1164

std_logic_1164

Package

waddr

waddr in std_logic_vector ( 11 DOWNTO 0 )

Port

wdata

wdata in std_logic_vector ( 31 DOWNTO 0 )

Port

we

we in std_logic

Port

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_if_flat.vhd