flat Architecture Reference

Processes
rx_reg_block	( mac_clk )
rst_macclk_block	( mac_clk )
rx_reg_block	( mac_clk )
rst_macclk_block	( mac_clk )
rx_reg_block	( mac_clk )
rst_macclk_block	( mac_clk )

Signals
addra	std_logic_vector ( 12 DOWNTO 0 )
addrb	std_logic_vector ( 12 DOWNTO 0 )
cksum	std_logic
clr_sum	std_logic
dia	std_logic_vector ( 7 DOWNTO 0 )
do_sum	std_logic
dob	std_logic_vector ( 7 DOWNTO 0 )
int_data	std_logic_vector ( 7 DOWNTO 0 )
int_valid	std_logic
outbyte	std_logic_vector ( 7 DOWNTO 0 )
payload_addr	std_logic_vector ( 12 DOWNTO 0 )
payload_data	std_logic_vector ( 7 DOWNTO 0 )
payload_send	std_logic
payload_we	std_logic
req_resend	std_logic
rx_reset	std_logic
rx_wea	std_logic
rxram_busy	std_logic
rxram_end_addr	std_logic_vector ( 12 DOWNTO 0 )
rxram_send	std_logic
udpaddrb	std_logic_vector ( 12 DOWNTO 0 )
udpdob	std_logic_vector ( 7 DOWNTO 0 )
udpram_busy	std_logic
udpram_send	std_logic
wea	std_logic
My_IP_addr_sig	std_logic_vector ( 31 DOWNTO 0 )
My_MAC_addr	std_logic_vector ( 47 DOWNTO 0 )
pkt_drop_rarp	std_logic
rarp_addr	std_logic_vector ( 12 DOWNTO 0 )
rarp_data	std_logic_vector ( 7 DOWNTO 0 )
rarp_end_addr	std_logic_vector ( 12 DOWNTO 0 )
rarp_mode	std_logic
rarp_send	std_logic
rarp_we	std_logic
arp_addr	std_logic_vector ( 12 DOWNTO 0 )
arp_data	std_logic_vector ( 7 DOWNTO 0 )
arp_end_addr	std_logic_vector ( 12 DOWNTO 0 )
arp_send	std_logic
arp_we	std_logic
rx_cksum	std_logic
rx_clr_sum	std_logic
clr_sum_payload	std_logic
clr_sum_ping	std_logic
rx_do_sum	std_logic
do_sum_payload	std_logic
do_sum_ping	std_logic
rx_int_data	std_logic_vector ( 7 DOWNTO 0 )
int_data_payload	std_logic_vector ( 7 DOWNTO 0 )
int_data_ping	std_logic_vector ( 7 DOWNTO 0 )
rx_int_valid	std_logic
int_valid_payload	std_logic
int_valid_ping	std_logic
rx_outbyte	std_logic_vector ( 7 DOWNTO 0 )
ping_addr	std_logic_vector ( 12 DOWNTO 0 )
ping_data	std_logic_vector ( 7 DOWNTO 0 )
ping_end_addr	std_logic_vector ( 12 DOWNTO 0 )
ping_send	std_logic
ping_we	std_logic
status_block	std_logic_vector ( 127 downto 0 )
status_request	std_logic
status_data	std_logic_vector ( 7 downto 0 )
status_addr	std_logic_vector ( 12 downto 0 )
status_we	std_logic
status_end_addr	std_logic_vector ( 12 downto 0 )
status_send	std_logic
pkt_drop_arp	std_logic
pkt_drop_payload	std_logic
pkt_drop_ping	std_logic
pkt_drop_resend	std_logic
pkt_drop_status	std_logic
pkt_runt	std_logic
rxpacket_ignored_sig	std_logic
my_rx_data	std_logic_vector ( 7 DOWNTO 0 )
my_rx_error	std_logic
my_rx_valid	std_logic
last_rx_last	std_logic
my_rx_last	std_logic
mac_tx_last_sig	std_logic
mac_tx_error_sig	std_logic
rst_macclk_reg	std_logic
ipbus_in_hdr	std_logic_vector ( 31 downto 0 )
ipbus_out_hdr	std_logic_vector ( 31 downto 0 )
pkt_broadcast	std_logic
ipbus_out_valid	std_logic
rxram_dropped_sig	std_logic
rxpayload_dropped_sig	std_logic
pkt_drop_ipbus	std_logic
reliable_packet	std_logic
pkt_byteswap	std_logic
next_pkt_id	std_logic_vector ( 15 downto 0 )
we_125	std_logic
rst_ipb_125	std_logic
rxram_write_buf	std_logic_vector ( INTERNALWIDTH - 1 downto 0 )
rxram_send_buf	std_logic_vector ( INTERNALWIDTH - 1 downto 0 )
rxram_sent	std_logic
internal_busy	std_logic
rxram_req_send	std_logic
rxram_send_x	std_logic
rxram_end_addr_x	std_logic_vector ( 12 downto 0 )
rxram_addra	std_logic_vector ( INTERNALWIDTH + ADDRWIDTH - 1 downto 0 )
rxram_addrb	std_logic_vector ( INTERNALWIDTH + ADDRWIDTH - 1 downto 0 )
rx_read_buffer	std_logic_vector ( BUFWIDTH - 1 downto 0 )
rx_read_buffer_125	std_logic_vector ( BUFWIDTH - 1 downto 0 )
rx_write_buffer	std_logic_vector ( BUFWIDTH - 1 downto 0 )
tx_read_buffer	std_logic_vector ( BUFWIDTH - 1 downto 0 )
tx_write_buffer	std_logic_vector ( BUFWIDTH - 1 downto 0 )
tx_write_buffer_125	std_logic_vector ( BUFWIDTH - 1 downto 0 )
resend_buf	std_logic_vector ( BUFWIDTH - 1 downto 0 )
rx_full_addra	std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )
tx_full_addrb	std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )
rx_full_addrb	std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )
tx_full_addra	std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )
pkt_resend	std_logic
pkt_rcvd	std_logic
rx_ram_busy	std_logic
rx_req_send_125	std_logic
udpram_sent	std_logic
busy_125	std_logic
enable_125	std_logic
rarp_125	std_logic
rx_ram_sent	std_logic
tx_ram_written	std_logic
rxreq_not_found	std_logic
resend_pkt_id	std_logic_vector ( 15 downto 0 )
clean_buf	std_logic_vector ( 2 ** BUFWIDTH - 1 downto 0 )

Instantiations
rarp_block	udp_rarp_block <Entity udp_rarp_block>
arp	udp_build_arp <Entity udp_build_arp>
ping	udp_build_ping <Entity udp_build_ping>
ipaddr	udp_ipaddr_block <Entity udp_ipaddr_block>
payload	udp_build_payload <Entity udp_build_payload>
resend	udp_build_resend <Entity udp_build_resend>
status	udp_build_status <Entity udp_build_status>
status_buffer	udp_status_buffer <Entity udp_status_buffer>
rx_byte_sum	udp_byte_sum <Entity udp_byte_sum>
rx_reset_block	udp_do_rx_reset <Entity udp_do_rx_reset>
rx_packet_parser	udp_packet_parser <Entity udp_packet_parser>
rx_ram_mux	udp_rxram_mux <Entity udp_rxram_mux>
internal_ram	udp_DualPortRAM <Entity udp_DualPortRAM>
internal_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
internal_ram_shim	udp_rxram_shim <Entity udp_rxram_shim>
ipbus_rx_ram	udp_DualPortRAM_rx <Entity udp_DualPortRAM_rx>
rx_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
rx_transactor	udp_rxtransactor_if <Entity udp_rxtransactor_if>
ipbus_tx_ram	udp_DualPortRAM_tx <Entity udp_DualPortRAM_tx>
tx_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
tx_byte_sum	udp_byte_sum <Entity udp_byte_sum>
tx_main	udp_tx_mux <Entity udp_tx_mux>
tx_transactor	udp_txtransactor_if <Entity udp_txtransactor_if>
clock_crossing_if	udp_clock_crossing_if <Entity udp_clock_crossing_if>
rarp_block	udp_rarp_block <Entity udp_rarp_block>
arp	udp_build_arp <Entity udp_build_arp>
ping	udp_build_ping <Entity udp_build_ping>
ipaddr	udp_ipaddr_block <Entity udp_ipaddr_block>
payload	udp_build_payload <Entity udp_build_payload>
resend	udp_build_resend <Entity udp_build_resend>
status	udp_build_status <Entity udp_build_status>
status_buffer	udp_status_buffer <Entity udp_status_buffer>
rx_byte_sum	udp_byte_sum <Entity udp_byte_sum>
rx_reset_block	udp_do_rx_reset <Entity udp_do_rx_reset>
rx_packet_parser	udp_packet_parser <Entity udp_packet_parser>
rx_ram_mux	udp_rxram_mux <Entity udp_rxram_mux>
internal_ram	udp_DualPortRAM <Entity udp_DualPortRAM>
internal_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
internal_ram_shim	udp_rxram_shim <Entity udp_rxram_shim>
ipbus_rx_ram	udp_DualPortRAM_rx <Entity udp_DualPortRAM_rx>
rx_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
rx_transactor	udp_rxtransactor_if <Entity udp_rxtransactor_if>
ipbus_tx_ram	udp_DualPortRAM_tx <Entity udp_DualPortRAM_tx>
tx_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
tx_byte_sum	udp_byte_sum <Entity udp_byte_sum>
tx_main	udp_tx_mux <Entity udp_tx_mux>
tx_transactor	udp_txtransactor_if <Entity udp_txtransactor_if>
clock_crossing_if	udp_clock_crossing_if <Entity udp_clock_crossing_if>
rarp_block	udp_rarp_block <Entity udp_rarp_block>
arp	udp_build_arp <Entity udp_build_arp>
ping	udp_build_ping <Entity udp_build_ping>
ipaddr	udp_ipaddr_block <Entity udp_ipaddr_block>
payload	udp_build_payload <Entity udp_build_payload>
resend	udp_build_resend <Entity udp_build_resend>
status	udp_build_status <Entity udp_build_status>
status_buffer	udp_status_buffer <Entity udp_status_buffer>
rx_byte_sum	udp_byte_sum <Entity udp_byte_sum>
rx_reset_block	udp_do_rx_reset <Entity udp_do_rx_reset>
rx_packet_parser	udp_packet_parser <Entity udp_packet_parser>
rx_ram_mux	udp_rxram_mux <Entity udp_rxram_mux>
internal_ram	udp_DualPortRAM <Entity udp_DualPortRAM>
internal_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
internal_ram_shim	udp_rxram_shim <Entity udp_rxram_shim>
ipbus_rx_ram	udp_DualPortRAM_rx <Entity udp_DualPortRAM_rx>
rx_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
rx_transactor	udp_rxtransactor_if <Entity udp_rxtransactor_if>
ipbus_tx_ram	udp_DualPortRAM_tx <Entity udp_DualPortRAM_tx>
tx_ram_selector	udp_buffer_selector <Entity udp_buffer_selector>
tx_byte_sum	udp_byte_sum <Entity udp_byte_sum>
tx_main	udp_tx_mux <Entity udp_tx_mux>
tx_transactor	udp_txtransactor_if <Entity udp_txtransactor_if>
clock_crossing_if	udp_clock_crossing_if <Entity udp_clock_crossing_if>

Member Function Documentation

rst_macclk_block() [1/3]

rst_macclk_block (   mac_clk   )

Process

rst_macclk_block() [2/3]

rst_macclk_block (   mac_clk   )

Process

rst_macclk_block() [3/3]

rst_macclk_block (   mac_clk   )

Process

rx_reg_block() [1/3]

rx_reg_block (   mac_clk   )

Process

rx_reg_block() [2/3]

rx_reg_block (   mac_clk   )

Process

rx_reg_block() [3/3]

rx_reg_block (   mac_clk   )

Process

Member Data Documentation

addra

addra std_logic_vector ( 12 DOWNTO 0 )

Signal

addrb

addrb std_logic_vector ( 12 DOWNTO 0 )

Signal

arp [1/3]

arp udp_build_arp

Instantiation

arp [2/3]

arp udp_build_arp

Instantiation

arp [3/3]

arp udp_build_arp

Instantiation

arp_addr

arp_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

arp_data

arp_data std_logic_vector ( 7 DOWNTO 0 )

Signal

arp_end_addr

arp_end_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

arp_send

arp_send std_logic

Signal

arp_we

arp_we std_logic

Signal

busy_125

busy_125 std_logic

Signal

cksum

cksum std_logic

Signal

clean_buf

clean_buf std_logic_vector ( 2 ** BUFWIDTH - 1 downto 0 )

Signal

clock_crossing_if [1/3]

clock_crossing_if udp_clock_crossing_if

Instantiation

clock_crossing_if [2/3]

clock_crossing_if udp_clock_crossing_if

Instantiation

clock_crossing_if [3/3]

clock_crossing_if udp_clock_crossing_if

Instantiation

clr_sum

clr_sum std_logic

Signal

clr_sum_payload

clr_sum_payload std_logic

Signal

clr_sum_ping

clr_sum_ping std_logic

Signal

dia

dia std_logic_vector ( 7 DOWNTO 0 )

Signal

do_sum

do_sum std_logic

Signal

do_sum_payload

do_sum_payload std_logic

Signal

do_sum_ping

do_sum_ping std_logic

Signal

dob

dob std_logic_vector ( 7 DOWNTO 0 )

Signal

enable_125

enable_125 std_logic

Signal

int_data

int_data std_logic_vector ( 7 DOWNTO 0 )

Signal

int_data_payload

int_data_payload std_logic_vector ( 7 DOWNTO 0 )

Signal

int_data_ping

int_data_ping std_logic_vector ( 7 DOWNTO 0 )

Signal

int_valid

int_valid std_logic

Signal

int_valid_payload

int_valid_payload std_logic

Signal

int_valid_ping

int_valid_ping std_logic

Signal

internal_busy

internal_busy std_logic

Signal

internal_ram [1/3]

internal_ram udp_DualPortRAM

Instantiation

internal_ram [2/3]

internal_ram udp_DualPortRAM

Instantiation

internal_ram [3/3]

internal_ram udp_DualPortRAM

Instantiation

internal_ram_selector [1/3]

internal_ram_selector udp_buffer_selector

Instantiation

internal_ram_selector [2/3]

internal_ram_selector udp_buffer_selector

Instantiation

internal_ram_selector [3/3]

internal_ram_selector udp_buffer_selector

Instantiation

internal_ram_shim [1/3]

internal_ram_shim udp_rxram_shim

Instantiation

internal_ram_shim [2/3]

internal_ram_shim udp_rxram_shim

Instantiation

internal_ram_shim [3/3]

internal_ram_shim udp_rxram_shim

Instantiation

ipaddr [1/3]

ipaddr udp_ipaddr_block

Instantiation

ipaddr [2/3]

ipaddr udp_ipaddr_block

Instantiation

ipaddr [3/3]

ipaddr udp_ipaddr_block

Instantiation

ipbus_in_hdr

ipbus_in_hdr std_logic_vector ( 31 downto 0 )

Signal

ipbus_out_hdr

ipbus_out_hdr std_logic_vector ( 31 downto 0 )

Signal

ipbus_out_valid

ipbus_out_valid std_logic

Signal

ipbus_rx_ram [1/3]

ipbus_rx_ram udp_DualPortRAM_rx

Instantiation

ipbus_rx_ram [2/3]

ipbus_rx_ram udp_DualPortRAM_rx

Instantiation

ipbus_rx_ram [3/3]

ipbus_rx_ram udp_DualPortRAM_rx

Instantiation

ipbus_tx_ram [1/3]

ipbus_tx_ram udp_DualPortRAM_tx

Instantiation

ipbus_tx_ram [2/3]

ipbus_tx_ram udp_DualPortRAM_tx

Instantiation

ipbus_tx_ram [3/3]

ipbus_tx_ram udp_DualPortRAM_tx

Instantiation

last_rx_last

last_rx_last std_logic

Signal

mac_tx_error_sig

mac_tx_error_sig std_logic

Signal

mac_tx_last_sig

mac_tx_last_sig std_logic

Signal

My_IP_addr_sig

My_IP_addr_sig std_logic_vector ( 31 DOWNTO 0 )

Signal

My_MAC_addr

My_MAC_addr std_logic_vector ( 47 DOWNTO 0 )

Signal

my_rx_data

my_rx_data std_logic_vector ( 7 DOWNTO 0 )

Signal

my_rx_error

my_rx_error std_logic

Signal

my_rx_last

my_rx_last std_logic

Signal

my_rx_valid

my_rx_valid std_logic

Signal

next_pkt_id

next_pkt_id std_logic_vector ( 15 downto 0 )

Signal

outbyte

outbyte std_logic_vector ( 7 DOWNTO 0 )

Signal

payload [1/3]

payload udp_build_payload

Instantiation

payload [2/3]

payload udp_build_payload

Instantiation

payload [3/3]

payload udp_build_payload

Instantiation

payload_addr

payload_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

payload_data

payload_data std_logic_vector ( 7 DOWNTO 0 )

Signal

payload_send

payload_send std_logic

Signal

payload_we

payload_we std_logic

Signal

ping [1/3]

ping udp_build_ping

Instantiation

ping [2/3]

ping udp_build_ping

Instantiation

ping [3/3]

ping udp_build_ping

Instantiation

ping_addr

ping_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

ping_data

ping_data std_logic_vector ( 7 DOWNTO 0 )

Signal

ping_end_addr

ping_end_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

ping_send

ping_send std_logic

Signal

ping_we

ping_we std_logic

Signal

pkt_broadcast

pkt_broadcast std_logic

Signal

pkt_byteswap

pkt_byteswap std_logic

Signal

pkt_drop_arp

pkt_drop_arp std_logic

Signal

pkt_drop_ipbus

pkt_drop_ipbus std_logic

Signal

pkt_drop_payload

pkt_drop_payload std_logic

Signal

pkt_drop_ping

pkt_drop_ping std_logic

Signal

pkt_drop_rarp

pkt_drop_rarp std_logic

Signal

pkt_drop_resend

pkt_drop_resend std_logic

Signal

pkt_drop_status

pkt_drop_status std_logic

Signal

pkt_rcvd

pkt_rcvd std_logic

Signal

pkt_resend

pkt_resend std_logic

Signal

pkt_runt

pkt_runt std_logic

Signal

rarp_125

rarp_125 std_logic

Signal

rarp_addr

rarp_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

rarp_block [1/3]

rarp_block udp_rarp_block

Instantiation

rarp_block [2/3]

rarp_block udp_rarp_block

Instantiation

rarp_block [3/3]

rarp_block udp_rarp_block

Instantiation

rarp_data

rarp_data std_logic_vector ( 7 DOWNTO 0 )

Signal

rarp_end_addr

rarp_end_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

rarp_mode

rarp_mode std_logic

Signal

rarp_send

rarp_send std_logic

Signal

rarp_we

rarp_we std_logic

Signal

reliable_packet

reliable_packet std_logic

Signal

req_resend

req_resend std_logic

Signal

resend [1/3]

resend udp_build_resend

Instantiation

resend [2/3]

resend udp_build_resend

Instantiation

resend [3/3]

resend udp_build_resend

Instantiation

resend_buf

resend_buf std_logic_vector ( BUFWIDTH - 1 downto 0 )

Signal

resend_pkt_id

resend_pkt_id std_logic_vector ( 15 downto 0 )

Signal

rst_ipb_125

rst_ipb_125 std_logic

Signal

rst_macclk_reg

rst_macclk_reg std_logic

Signal

rx_byte_sum [1/3]

rx_byte_sum udp_byte_sum

Instantiation

rx_byte_sum [2/3]

rx_byte_sum udp_byte_sum

Instantiation

rx_byte_sum [3/3]

rx_byte_sum udp_byte_sum

Instantiation

rx_cksum

rx_cksum std_logic

Signal

rx_clr_sum

rx_clr_sum std_logic

Signal

rx_do_sum

rx_do_sum std_logic

Signal

rx_full_addra

rx_full_addra std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )

Signal

rx_full_addrb

rx_full_addrb std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )

Signal

rx_int_data

rx_int_data std_logic_vector ( 7 DOWNTO 0 )

Signal

rx_int_valid

rx_int_valid std_logic

Signal

rx_outbyte

rx_outbyte std_logic_vector ( 7 DOWNTO 0 )

Signal

rx_packet_parser [1/3]

rx_packet_parser udp_packet_parser

Instantiation

rx_packet_parser [2/3]

rx_packet_parser udp_packet_parser

Instantiation

rx_packet_parser [3/3]

rx_packet_parser udp_packet_parser

Instantiation

rx_ram_busy

rx_ram_busy std_logic

Signal

rx_ram_mux [1/3]

rx_ram_mux udp_rxram_mux

Instantiation

rx_ram_mux [2/3]

rx_ram_mux udp_rxram_mux

Instantiation

rx_ram_mux [3/3]

rx_ram_mux udp_rxram_mux

Instantiation

rx_ram_selector [1/3]

rx_ram_selector udp_buffer_selector

Instantiation

rx_ram_selector [2/3]

rx_ram_selector udp_buffer_selector

Instantiation

rx_ram_selector [3/3]

rx_ram_selector udp_buffer_selector

Instantiation

rx_ram_sent

rx_ram_sent std_logic

Signal

rx_read_buffer

rx_read_buffer std_logic_vector ( BUFWIDTH - 1 downto 0 )

Signal

rx_read_buffer_125

rx_read_buffer_125 std_logic_vector ( BUFWIDTH - 1 downto 0 )

Signal

rx_req_send_125

rx_req_send_125 std_logic

Signal

rx_reset

rx_reset std_logic

Signal

rx_reset_block [1/3]

rx_reset_block udp_do_rx_reset

Instantiation

rx_reset_block [2/3]

rx_reset_block udp_do_rx_reset

Instantiation

rx_reset_block [3/3]

rx_reset_block udp_do_rx_reset

Instantiation

rx_transactor [1/3]

rx_transactor udp_rxtransactor_if

Instantiation

rx_transactor [2/3]

rx_transactor udp_rxtransactor_if

Instantiation

rx_transactor [3/3]

rx_transactor udp_rxtransactor_if

Instantiation

rx_wea

rx_wea std_logic

Signal

rx_write_buffer

rx_write_buffer std_logic_vector ( BUFWIDTH - 1 downto 0 )

Signal

rxpacket_ignored_sig

rxpacket_ignored_sig std_logic

Signal

rxpayload_dropped_sig

rxpayload_dropped_sig std_logic

Signal

rxram_addra

rxram_addra std_logic_vector ( INTERNALWIDTH + ADDRWIDTH - 1 downto 0 )

Signal

rxram_addrb

rxram_addrb std_logic_vector ( INTERNALWIDTH + ADDRWIDTH - 1 downto 0 )

Signal

rxram_busy

rxram_busy std_logic

Signal

rxram_dropped_sig

rxram_dropped_sig std_logic

Signal

rxram_end_addr

rxram_end_addr std_logic_vector ( 12 DOWNTO 0 )

Signal

rxram_end_addr_x

rxram_end_addr_x std_logic_vector ( 12 downto 0 )

Signal

rxram_req_send

rxram_req_send std_logic

Signal

rxram_send

rxram_send std_logic

Signal

rxram_send_buf

rxram_send_buf std_logic_vector ( INTERNALWIDTH - 1 downto 0 )

Signal

rxram_send_x

rxram_send_x std_logic

Signal

rxram_sent

rxram_sent std_logic

Signal

rxram_write_buf

rxram_write_buf std_logic_vector ( INTERNALWIDTH - 1 downto 0 )

Signal

rxreq_not_found

rxreq_not_found std_logic

Signal

status [1/3]

status udp_build_status

Instantiation

status [2/3]

status udp_build_status

Instantiation

status [3/3]

status udp_build_status

Instantiation

status_addr

status_addr std_logic_vector ( 12 downto 0 )

Signal

status_block

status_block std_logic_vector ( 127 downto 0 )

Signal

status_buffer [1/3]

status_buffer udp_status_buffer

Instantiation

status_buffer [2/3]

status_buffer udp_status_buffer

Instantiation

status_buffer [3/3]

status_buffer udp_status_buffer

Instantiation

status_data

status_data std_logic_vector ( 7 downto 0 )

Signal

status_end_addr

status_end_addr std_logic_vector ( 12 downto 0 )

Signal

status_request

status_request std_logic

Signal

status_send

status_send std_logic

Signal

status_we

status_we std_logic

Signal

tx_byte_sum [1/3]

tx_byte_sum udp_byte_sum

Instantiation

tx_byte_sum [2/3]

tx_byte_sum udp_byte_sum

Instantiation

tx_byte_sum [3/3]

tx_byte_sum udp_byte_sum

Instantiation

tx_full_addra

tx_full_addra std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )

Signal

tx_full_addrb

tx_full_addrb std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )

Signal

tx_main [1/3]

tx_main udp_tx_mux

Instantiation

tx_main [2/3]

tx_main udp_tx_mux

Instantiation

tx_main [3/3]

tx_main udp_tx_mux

Instantiation

tx_ram_selector [1/3]

tx_ram_selector udp_buffer_selector

Instantiation

tx_ram_selector [2/3]

tx_ram_selector udp_buffer_selector

Instantiation

tx_ram_selector [3/3]

tx_ram_selector udp_buffer_selector

Instantiation

tx_ram_written

tx_ram_written std_logic

Signal

tx_read_buffer

tx_read_buffer std_logic_vector ( BUFWIDTH - 1 downto 0 )

Signal

tx_transactor [1/3]

tx_transactor udp_txtransactor_if

Instantiation

tx_transactor [2/3]

tx_transactor udp_txtransactor_if

Instantiation

tx_transactor [3/3]

tx_transactor udp_txtransactor_if

Instantiation

tx_write_buffer

tx_write_buffer std_logic_vector ( BUFWIDTH - 1 downto 0 )

Signal

tx_write_buffer_125

tx_write_buffer_125 std_logic_vector ( BUFWIDTH - 1 downto 0 )

Signal

udpaddrb

udpaddrb std_logic_vector ( 12 DOWNTO 0 )

Signal

udpdob

udpdob std_logic_vector ( 7 DOWNTO 0 )

Signal

udpram_busy

udpram_busy std_logic

Signal

udpram_send

udpram_send std_logic

Signal

udpram_sent

udpram_sent std_logic

Signal

we_125

we_125 std_logic

Signal

wea

wea std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_if_flat.vhd